JPS63146772U - - Google Patents
Info
- Publication number
- JPS63146772U JPS63146772U JP4018787U JP4018787U JPS63146772U JP S63146772 U JPS63146772 U JP S63146772U JP 4018787 U JP4018787 U JP 4018787U JP 4018787 U JP4018787 U JP 4018787U JP S63146772 U JPS63146772 U JP S63146772U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- control
- shift register
- provides
- low level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図に示す制御信号設定用シフトレ
ジスタの一実施例を示す図、第３図は従来の集積
回路を示すブロツク図である。
図において、１は集積回路、８は出力固定制御
ゲート、９は外部制御端子、１０は制御信号設定
用シフトレジスタ、１１はシリアルデータ入力端
子、１２は制御信号リセツト端子、１３はフリツ
プフロツプ、１４はシリアルデータ入力信号、１
５は制御信号リセツト信号、１６は出力固定信号
である。なお、図中同一符号は同一又は相当部分
を示す。
FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a diagram showing an embodiment of the control signal setting shift register shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional integrated circuit. It is. In the figure, 1 is an integrated circuit, 8 is a fixed output control gate, 9 is an external control terminal, 10 is a shift register for setting control signals, 11 is a serial data input terminal, 12 is a control signal reset terminal, 13 is a flip-flop, and 14 is a Serial data input signal, 1
5 is a control signal reset signal, and 16 is an output fixing signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
）レベル又はロウ（Ｌｏｗ）レベルに固定する複
数の出力固定制御ゲートと、上記複数の出力固定
制御ゲートの全てを同時にハイレベル又はロウレ
ベルに固定するための制御信号を与える外部制御
端子と、上記複数の出力固定制御ゲートをハイレ
ベル又はロウレベルに固定する制御信号を与える
制御信号設定用シフトレジスタと、上記制御信号
設定用シフトレジスタへシリアルデータを与える
シリアルデータ入力端子と、上記制御信号設定用
シフトレジスタで設定された制御信号を解除する
制御信号リセツト端子とを備えたことを特徴とす
る集積回路。 The output value is set to High by the required control signal.
) a plurality of output fixed control gates fixed to a high level or a low level; an external control terminal that provides a control signal for simultaneously fixing all of the plurality of output fixed control gates to a high level or a low level; a control signal setting shift register that provides a control signal to fix the output fixed control gate of the control gate to a high level or a low level, a serial data input terminal that provides serial data to the control signal setting shift register, and the control signal setting shift register. An integrated circuit comprising: a control signal reset terminal for canceling a control signal set in the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4018787U JPS63146772U (en) | 1987-03-19 | 1987-03-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4018787U JPS63146772U (en) | 1987-03-19 | 1987-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63146772U true JPS63146772U (en) | 1988-09-28 |
Family
ID=30854049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4018787U Pending JPS63146772U (en) | 1987-03-19 | 1987-03-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63146772U (en) |
-
1987
- 1987-03-19 JP JP4018787U patent/JPS63146772U/ja active Pending
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