JPS58184437U - Paper ejection error detection device - Google Patents
Paper ejection error detection deviceInfo
- Publication number
- JPS58184437U JPS58184437U JP7987682U JP7987682U JPS58184437U JP S58184437 U JPS58184437 U JP S58184437U JP 7987682 U JP7987682 U JP 7987682U JP 7987682 U JP7987682 U JP 7987682U JP S58184437 U JPS58184437 U JP S58184437U
- Authority
- JP
- Japan
- Prior art keywords
- input
- detection device
- paper ejection
- paper
- error detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Paper Feeding For Electrophotography (AREA)
- Controlling Sheets Or Webs (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は印刷機の要部の簡略構成図、第２図は本考案に
係る制御ブロック図、第３図はタイミングチャートであ
る。
６・・・・・・光検知器、７・・・・・・給紙信号発生
回路、９・・・・・・反転器、１０・・・・・・微分回
路、１１・・・・・・ＤＱフリップフロップ、１２・・
・・・・アンドゲート。FIG. 1 is a simplified configuration diagram of the main parts of the printing press, FIG. 2 is a control block diagram according to the present invention, and FIG. 3 is a timing chart. 6...Photodetector, 7...Paper feed signal generation circuit, 9...Inverter, 10...Differential circuit, 11...・DQ flip-flop, 12...
...and gate.
Claims (1)
回路と、給紙信号を入力する反転器と、この反転器から
の出力をクワツク入力とし、また排紙信号を入力とする
微分回路からの出力をクリア入力とするＤＱフリップフ
ロップと、給紙信号発生回路からの出力信号を１つの入
力条件とし他の入力条件をＤＱフリップフロップ出力信
号とするアンドゲートからなる排紙ミス検出装置。A reflective photodetector installed in the paper ejection section, a paper feed signal generation circuit, an inverter that inputs the paper feed signal, the output from this inverter is used as a quack input, and the paper ejection signal is used as an input. A paper discharge error consisting of a DQ flip-flop that uses the output from the differentiating circuit as a clear input, and an AND gate that uses the output signal from the paper feed signal generation circuit as one input condition and the other input condition as the DQ flip-flop output signal. Detection device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7987682U JPS58184437U (en) | 1982-06-01 | 1982-06-01 | Paper ejection error detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7987682U JPS58184437U (en) | 1982-06-01 | 1982-06-01 | Paper ejection error detection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58184437U true JPS58184437U (en) | 1983-12-08 |
Family
ID=30089048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7987682U Pending JPS58184437U (en) | 1982-06-01 | 1982-06-01 | Paper ejection error detection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58184437U (en) |
-
1982
- 1982-06-01 JP JP7987682U patent/JPS58184437U/en active Pending
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