JPS60101154U - Data output control circuit - Google Patents

Data output control circuit

Info

Publication number
JPS60101154U
JPS60101154U JP19439483U JP19439483U JPS60101154U JP S60101154 U JPS60101154 U JP S60101154U JP 19439483 U JP19439483 U JP 19439483U JP 19439483 U JP19439483 U JP 19439483U JP S60101154 U JPS60101154 U JP S60101154U
Authority
JP
Japan
Prior art keywords
signal
output control
control circuit
data output
printer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19439483U
Other languages
Japanese (ja)
Inventor
河野 磐生
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP19439483U priority Critical patent/JPS60101154U/en
Publication of JPS60101154U publication Critical patent/JPS60101154U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案データ出力制御回路のブロック図、第2
図は第1図の回路の動作を説明するためのタイミソグチ
ヤードである。 3・・・第2のフリップフロップ回路、5・・・ラッチ
回路、14−・・シフトレジスタ。
Figure 1 is a block diagram of the data output control circuit of the present invention;
The figure is a timing chart for explaining the operation of the circuit of FIG. 1. 3... Second flip-flop circuit, 5... Latch circuit, 14-... Shift register.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パラレルな状態でプリンタに送り出される印字データの
送出タイミングを制御するデータ出力制御回路において
、上記印字データを書込信号の入力によりプリンタ側へ
送出開始するラッチ回路と、上記書込信号によるパルス
信号が入力され、クロック信号によりこのパルス信号を
複数段シフトしてから上記ラッチ回路へ印字データの送
出を禁止する禁止信号として印加するシフトレジスタと
、から成り、上記シフトレジスタは上記クロック信号の
タイミングでシフトされるパルス信号シフト中間位置で
ストローブ信号でプリンタへ送出することを特徴とした
データ出力制御回路。
A data output control circuit that controls the sending timing of print data sent to the printer in parallel includes a latch circuit that starts sending the print data to the printer upon input of a write signal, and a pulse signal generated by the write signal. a shift register that shifts this pulse signal by multiple stages according to a clock signal and then applies it to the latch circuit as an inhibition signal that prohibits the sending of print data, and the shift register shifts the pulse signal at the timing of the clock signal. A data output control circuit characterized in that a strobe signal is sent to a printer at an intermediate position of a pulse signal shift.
JP19439483U 1983-12-16 1983-12-16 Data output control circuit Pending JPS60101154U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19439483U JPS60101154U (en) 1983-12-16 1983-12-16 Data output control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19439483U JPS60101154U (en) 1983-12-16 1983-12-16 Data output control circuit

Publications (1)

Publication Number Publication Date
JPS60101154U true JPS60101154U (en) 1985-07-10

Family

ID=30417849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19439483U Pending JPS60101154U (en) 1983-12-16 1983-12-16 Data output control circuit

Country Status (1)

Country Link
JP (1) JPS60101154U (en)

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