JPS58152029U - Narrow pulse generation circuit - Google Patents

Narrow pulse generation circuit

Info

Publication number
JPS58152029U
JPS58152029U JP4883382U JP4883382U JPS58152029U JP S58152029 U JPS58152029 U JP S58152029U JP 4883382 U JP4883382 U JP 4883382U JP 4883382 U JP4883382 U JP 4883382U JP S58152029 U JPS58152029 U JP S58152029U
Authority
JP
Japan
Prior art keywords
pulse generation
generation circuit
narrow pulse
output signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4883382U
Other languages
Japanese (ja)
Inventor
小神 長次
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP4883382U priority Critical patent/JPS58152029U/en
Publication of JPS58152029U publication Critical patent/JPS58152029U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の狭幅パルス発生回路、第2図は本考案の
第1実施例の狭幅パルス発生回路、第3図は第2図の狭
幅パルス発生回路におけるタイムチャート、第4図は本
考案の第2実施例の狭幅パルス発生回路、第5図は第4
図の狭幅パルス発生回路におけるタイムチャートを示す
。 1・・・D型フリップフロップ、2・・・否定回路、3
・・・入力端子、4・・・出力端子。
Fig. 1 shows a conventional narrow-width pulse generation circuit, Fig. 2 shows a narrow-width pulse generation circuit according to the first embodiment of the present invention, Fig. 3 shows a time chart for the narrow-width pulse generation circuit of Fig. 2, and Fig. 4 5 is a narrow width pulse generating circuit according to a second embodiment of the present invention, and FIG.
3 shows a time chart in the narrow pulse generation circuit shown in the figure. 1...D-type flip-flop, 2...Negation circuit, 3
...Input terminal, 4...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デジタル信号用の論理回路において、LOWレベルから
HIGHレベルへ変化する入力信号をタイミング入力と
するとともに、出力信号あるいは出力信号の反転信号を
直接もしくは否定回路を介してセット入力もしくはリセ
ット入力として帰還させ、瞬時に出力信号のレベルをも
との状態に戻すD型フリップフロップを備えた狭幅パル
ス発生回路。
In a logic circuit for digital signals, an input signal changing from a LOW level to a HIGH level is used as a timing input, and an output signal or an inverted signal of the output signal is fed back as a set input or a reset input directly or via an inverting circuit, A narrow pulse generation circuit equipped with a D-type flip-flop that instantly returns the output signal level to its original state.
JP4883382U 1982-04-06 1982-04-06 Narrow pulse generation circuit Pending JPS58152029U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4883382U JPS58152029U (en) 1982-04-06 1982-04-06 Narrow pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4883382U JPS58152029U (en) 1982-04-06 1982-04-06 Narrow pulse generation circuit

Publications (1)

Publication Number Publication Date
JPS58152029U true JPS58152029U (en) 1983-10-12

Family

ID=30059733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4883382U Pending JPS58152029U (en) 1982-04-06 1982-04-06 Narrow pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS58152029U (en)

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