JPS5830362U - Pulse receiver circuit - Google Patents
Pulse receiver circuitInfo
- Publication number
- JPS5830362U JPS5830362U JP12404381U JP12404381U JPS5830362U JP S5830362 U JPS5830362 U JP S5830362U JP 12404381 U JP12404381 U JP 12404381U JP 12404381 U JP12404381 U JP 12404381U JP S5830362 U JPS5830362 U JP S5830362U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- output
- receiver circuit
- pulse receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の受信回路のブロック図、第２図はその波
形図、第３図は従来の他の受信回路のブロック図、第４
図は本考案の受信回路のブロック図、第５図及び第６図
はそのタイミングチャートを、各々表わす。
３・・・・・・パルス発生器、４．５・・・・・・フリ
ップフロップ、６・・・・・・遅延回路、７・・・・・
・微分回路。Figure 1 is a block diagram of a conventional receiving circuit, Figure 2 is its waveform diagram, Figure 3 is a block diagram of another conventional receiving circuit, and Figure 4 is a block diagram of another conventional receiving circuit.
The figure shows a block diagram of the receiving circuit of the present invention, and FIGS. 5 and 6 show its timing charts, respectively. 3...Pulse generator, 4.5...Flip-flop, 6...Delay circuit, 7...
・Differential circuit.
Claims (1)
送されてくるパルス信号により該フリップフロップが反
転されるようにし、一方のフリップフロップの出力端子
より発生される出力を所定゛ 時間遅延して各フリ
ップフロップを再度反転させるようにすると共に、他の
フリップフロップの出力端子より発生される出力を伝送
されているパルス信号の出力信号とすることを特徴とす
るパルス受信回路。A flip-flop is connected to each of the two transmission lines so that the flip-flop is inverted by the transmitted pulse signal, and the output generated from the output terminal of one of the flip-flops is delayed by a predetermined time and then output to each flip-flop. What is claimed is: 1. A pulse receiving circuit characterized by inverting the flip-flop again and using the output generated from the output terminal of another flip-flop as the output signal of the pulse signal being transmitted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12404381U JPS5830362U (en) | 1981-08-24 | 1981-08-24 | Pulse receiver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12404381U JPS5830362U (en) | 1981-08-24 | 1981-08-24 | Pulse receiver circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5830362U true JPS5830362U (en) | 1983-02-28 |
Family
ID=29917931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12404381U Pending JPS5830362U (en) | 1981-08-24 | 1981-08-24 | Pulse receiver circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5830362U (en) |
-
1981
- 1981-08-24 JP JP12404381U patent/JPS5830362U/en active Pending
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