JPS60145738U - Synchronous circuit for asynchronous signals and pulse signals - Google Patents
Synchronous circuit for asynchronous signals and pulse signalsInfo
- Publication number
- JPS60145738U JPS60145738U JP3460484U JP3460484U JPS60145738U JP S60145738 U JPS60145738 U JP S60145738U JP 3460484 U JP3460484 U JP 3460484U JP 3460484 U JP3460484 U JP 3460484U JP S60145738 U JPS60145738 U JP S60145738U
- Authority
- JP
- Japan
- Prior art keywords
- asynchronous
- signal
- signals
- circuit
- synchronous circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は従来の同期回路の概略図、第３図は
本考案の一実施例を示した非同期信号とパルス信号を同
期させる回路の概略図、第４間尺 。
び第５図は信号波形図である。
１′・・・・・・第１Ｄフリツプフロツプ回路、３・・
・・・・遅、低回路、４・・・・・・アンド回路。
第４図
第５図1 and 2 are schematic diagrams of a conventional synchronization circuit, and FIG. 3 is a schematic diagram of a circuit for synchronizing an asynchronous signal and a pulse signal according to an embodiment of the present invention. and FIG. 5 are signal waveform diagrams. 1'... 1st D flip-flop circuit, 3...
...Slow, low circuit, 4...AND circuit. Figure 4 Figure 5
Claims (1)
ルス信号の同期信号を発生するフリップフロップ回路、
前記フリップフロップ回路に入力される非同期信号を適
宜時間遅らせる遅延回路、前記フリップフロップ回路の
出力信号と該遅延回路の出力信号を入力とするアンド回
路とから成る非同期信号とパルス信号の同期回路。a flip-flop circuit that receives an asynchronous signal and a pulse signal and generates a synchronous signal of the asynchronous signal and the pulse signal;
An asynchronous signal and pulse signal synchronization circuit comprising a delay circuit for appropriately delaying an asynchronous signal input to the flip-flop circuit, and an AND circuit inputting an output signal of the flip-flop circuit and an output signal of the delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3460484U JPS60145738U (en) | 1984-03-10 | 1984-03-10 | Synchronous circuit for asynchronous signals and pulse signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3460484U JPS60145738U (en) | 1984-03-10 | 1984-03-10 | Synchronous circuit for asynchronous signals and pulse signals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60145738U true JPS60145738U (en) | 1985-09-27 |
Family
ID=30538127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3460484U Pending JPS60145738U (en) | 1984-03-10 | 1984-03-10 | Synchronous circuit for asynchronous signals and pulse signals |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60145738U (en) |
-
1984
- 1984-03-10 JP JP3460484U patent/JPS60145738U/en active Pending
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