JPS59121955U - Data sampling signal generation circuit - Google Patents
Data sampling signal generation circuitInfo
- Publication number
- JPS59121955U JPS59121955U JP1641883U JP1641883U JPS59121955U JP S59121955 U JPS59121955 U JP S59121955U JP 1641883 U JP1641883 U JP 1641883U JP 1641883 U JP1641883 U JP 1641883U JP S59121955 U JPS59121955 U JP S59121955U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data sampling
- data
- generation circuit
- sampling signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は各信号のタイムチャートを、第２図ａは従来の
回路を、第２図すは本考案の一実施例の回路を示す。
１及び８・・・タイミング信号入力端子、２及び７・・
・フレーム信号入力端子、３．５． １０・・・ＡＮＤ
ゲート、４・・・シフトレジスタ、６・・・内部クロッ
ク発生回路、９・・・フリップフロップ。FIG. 1 shows a time chart of each signal, FIG. 2a shows a conventional circuit, and FIG. 2 shows a circuit according to an embodiment of the present invention. 1 and 8...timing signal input terminals, 2 and 7...
・Frame signal input terminal, 3.5. 10...AND
Gate, 4...Shift register, 6...Internal clock generation circuit, 9...Flip-flop.
Claims (1)
同期したデータ及びデータ送信中を示すフレーム信号の
三種の信号を用いた直列同期伝送方式によるデータ受信
回路において、前記フレーム信号を前記タイミング信号
の半相分遅延させる遅延手段と、前記タイミング信号、
前記フレーム信号及び、前記遅延手段により作成される
第二のフレーム信号の三者の論理積をとるゲート手段と
・を具備して成ることを特徴とするデータサンプリング
信号発生回路。In a data receiving circuit using a serial synchronous transmission method that uses three types of signals: a constantly input timing signal, data synchronized with this timing signal, and a frame signal indicating that data is being transmitted, the frame signal is divided into half phases of the timing signal. a delay means for delaying the timing signal;
A data sampling signal generating circuit comprising: gate means for performing an AND operation on the frame signal and the second frame signal generated by the delay means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1641883U JPS59121955U (en) | 1983-02-07 | 1983-02-07 | Data sampling signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1641883U JPS59121955U (en) | 1983-02-07 | 1983-02-07 | Data sampling signal generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59121955U true JPS59121955U (en) | 1984-08-16 |
Family
ID=30147703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1641883U Pending JPS59121955U (en) | 1983-02-07 | 1983-02-07 | Data sampling signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121955U (en) |
-
1983
- 1983-02-07 JP JP1641883U patent/JPS59121955U/en active Pending
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