JPS59192742U - data processing circuit - Google Patents
data processing circuitInfo
- Publication number
- JPS59192742U JPS59192742U JP8644383U JP8644383U JPS59192742U JP S59192742 U JPS59192742 U JP S59192742U JP 8644383 U JP8644383 U JP 8644383U JP 8644383 U JP8644383 U JP 8644383U JP S59192742 U JPS59192742 U JP S59192742U
- Authority
- JP
- Japan
- Prior art keywords
- data
- inputting
- synchronization
- control signal
- data processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来回路を示す回路図、第２図は第１図回路で
用いられる信号のタイミングチャート、第３図はこの考
案に係るデータ処理回路の△実施例を示す回路図、第４
図は第３図回路で用いられる信号のタイミングチャート
である。
３１．３３，３４，４１，４３．４４・・・クロック同
期型反転回路（クロックドインバータ）、３２．４２・
・・処理回路、３５． ３７． ４５． ４７・・・イ
ンバータ、３６．４６・・・遅延回路。FIG. 1 is a circuit diagram showing a conventional circuit, FIG. 2 is a timing chart of signals used in the circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing an embodiment of the data processing circuit according to this invention, and FIG.
The figure is a timing chart of signals used in the circuit of Figure 3. 31.33, 34, 41, 43.44... Clock synchronous inverter circuit (clocked inverter), 32.42.
...processing circuit, 35. 37. 45. 47...Inverter, 36.46...Delay circuit.
Claims (1)
ぞれ所定時間遅延して第３、第４の制御信号を得る手段
と、上記第１の制御信号に同期してデータを入力しデー
タ入力後は所定の処理を行ない処理後のデータを上記第
４の制御信号に同期して出力する手段と、上記第２の制
御信号に同期してデータを入力しデータ入力後は所定の
処理を行ない処理後のデータを上記第３の制御信号に同
期して出力する手段とを具備したことを特徴とするデー
タ処理回路。, means for obtaining third and fourth control signals by respectively delaying first and second control signals having different phases by a predetermined time, and means for inputting data in synchronization with the first control signal and for inputting data after inputting the data. means for performing predetermined processing and outputting the processed data in synchronization with the fourth control signal; and means for inputting data in synchronization with the second control signal and performing predetermined processing after inputting the data. and means for outputting subsequent data in synchronization with the third control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8644383U JPS59192742U (en) | 1983-06-07 | 1983-06-07 | data processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8644383U JPS59192742U (en) | 1983-06-07 | 1983-06-07 | data processing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59192742U true JPS59192742U (en) | 1984-12-21 |
Family
ID=30216374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8644383U Pending JPS59192742U (en) | 1983-06-07 | 1983-06-07 | data processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59192742U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5120647A (en) * | 1974-08-13 | 1976-02-19 | Hitachi Ltd | Ronrisochino dosataimingusetsuteihoshiki |
-
1983
- 1983-06-07 JP JP8644383U patent/JPS59192742U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5120647A (en) * | 1974-08-13 | 1976-02-19 | Hitachi Ltd | Ronrisochino dosataimingusetsuteihoshiki |
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