JPS596354U - Fault detection device in data transmission - Google Patents
Fault detection device in data transmissionInfo
- Publication number
- JPS596354U JPS596354U JP9930882U JP9930882U JPS596354U JP S596354 U JPS596354 U JP S596354U JP 9930882 U JP9930882 U JP 9930882U JP 9930882 U JP9930882 U JP 9930882U JP S596354 U JPS596354 U JP S596354U
- Authority
- JP
- Japan
- Prior art keywords
- detection device
- data transmission
- fault detection
- transmission
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のＣＰＵユニットと増設ユニットの伝送方
式を示すブロック図、第２図は本考案の一実施例を示す
ブロック図、第３図は伝送フォーマットを示す図、第４
図は故障検出回路である。
ｌ ；ＣＰＵ（基本）ユニット、２；伝送ケーブル、３
；Ｐｌｏ（増設）ユニット、４；送信ライン、５；受
信ライン、１１；受信ライン、１２；シフトレジスタ、
１３；同期信号検出回路、１４；同期信号検出レジスタ
、１５；同期信号未検出レジスタ、１６；警報出力、１
７；受信アドレスラッチレジスタ、１８ニアドレスデコ
ーダ、１９；データバス、２０；反転連送エラーレジス
タ、２１；アドレスデコーダ、２２；タイミング回路。Fig. 1 is a block diagram showing a conventional transmission method between a CPU unit and an expansion unit, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing a transmission format, and Fig. 4 is a block diagram showing a transmission method of a conventional CPU unit and an expansion unit.
The figure shows a failure detection circuit. l; CPU (basic) unit, 2; transmission cable, 3
; Plo (extension) unit, 4; Transmission line, 5; Reception line, 11; Reception line, 12; Shift register,
13; Synchronous signal detection circuit, 14; Synchronous signal detection register, 15; Synchronous signal non-detection register, 16; Alarm output, 1
7; reception address latch register, 18 near address decoder, 19; data bus, 20; inverted continuous transmission error register, 21; address decoder, 22; timing circuit.
Claims (1)
採用して成るデータ伝送における故障検出装置。A failure detection device in data transmission that employs serial transmission in the transmission section between the arithmetic processing section and the input/output section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9930882U JPS596354U (en) | 1982-07-02 | 1982-07-02 | Fault detection device in data transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9930882U JPS596354U (en) | 1982-07-02 | 1982-07-02 | Fault detection device in data transmission |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS596354U true JPS596354U (en) | 1984-01-17 |
Family
ID=30235400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9930882U Pending JPS596354U (en) | 1982-07-02 | 1982-07-02 | Fault detection device in data transmission |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596354U (en) |
-
1982
- 1982-07-02 JP JP9930882U patent/JPS596354U/en active Pending
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