JPS59111349U - Data error prevention circuit in receiver - Google Patents

Data error prevention circuit in receiver

Info

Publication number
JPS59111349U
JPS59111349U JP327983U JP327983U JPS59111349U JP S59111349 U JPS59111349 U JP S59111349U JP 327983 U JP327983 U JP 327983U JP 327983 U JP327983 U JP 327983U JP S59111349 U JPS59111349 U JP S59111349U
Authority
JP
Japan
Prior art keywords
receiver
data
prevention circuit
error prevention
data error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP327983U
Other languages
Japanese (ja)
Inventor
藤沢　利之
Original Assignee
株式会社ケンウッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ケンウッド filed Critical 株式会社ケンウッド
Priority to JP327983U priority Critical patent/JPS59111349U/en
Publication of JPS59111349U publication Critical patent/JPS59111349U/en
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案に係る受信機におけるデータ誤り防止回路
の実施例を示し、第１図はブロック図、第２薗は動作説
明図である。　　　□ ２：送受信機、３：演算処理装置、５ニスイツチング部
、９：検出部。The drawings show an embodiment of a data error prevention circuit in a receiver according to the present invention, with FIG. 1 being a block diagram and FIG. 2 being an operation explanatory diagram. □ 2: Transmitter/receiver, 3: Arithmetic processing unit, 5 Niswitching section, 9: Detection section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 受信機から出力されたデータ信号中のブロック長信号を
検出することにより、そのデータの終了時期を検知する
検出部と、該検出部からのデータ終了信号により制御さ
れ、受信機からの演算処理装置へのデータ信号入力を遮
断するようになっているスイッチング部とを備え、デー
タの終了時期に同期させて上記演算処理装置への入力信
号を遮断するように構成されている。ことを特徴とする
受信機におけるデータ誤り防止回路。a detection unit that detects the end time of the data by detecting a block length signal in the data signal output from the receiver; and an arithmetic processing unit that is controlled by the data end signal from the detection unit and output from the receiver. and a switching section configured to cut off data signal input to the arithmetic processing unit, and is configured to cut off the input signal to the arithmetic processing unit in synchronization with the end time of data. A data error prevention circuit in a receiver, characterized in that:
JP327983U 1983-01-17 1983-01-17 Data error prevention circuit in receiver Pending JPS59111349U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP327983U JPS59111349U (en) 1983-01-17 1983-01-17 Data error prevention circuit in receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP327983U JPS59111349U (en) 1983-01-17 1983-01-17 Data error prevention circuit in receiver

Publications (1)

Publication Number Publication Date
JPS59111349U true JPS59111349U (en) 1984-07-27

Family

ID=30134904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP327983U Pending JPS59111349U (en) 1983-01-17 1983-01-17 Data error prevention circuit in receiver

Country Status (1)

Country Link
JP (1) JPS59111349U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS585061A (en) * 1981-06-30 1983-01-12 Fujitsu Ltd Multidrop transmission system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS585061A (en) * 1981-06-30 1983-01-12 Fujitsu Ltd Multidrop transmission system

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