JPS5956577U - Generated signal detection device - Google Patents
Generated signal detection deviceInfo
- Publication number
- JPS5956577U JPS5956577U JP15084782U JP15084782U JPS5956577U JP S5956577 U JPS5956577 U JP S5956577U JP 15084782 U JP15084782 U JP 15084782U JP 15084782 U JP15084782 U JP 15084782U JP S5956577 U JPS5956577 U JP S5956577U
- Authority
- JP
- Japan
- Prior art keywords
- wave device
- band
- signal
- conversion circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による一実施例の構成を示すブロック図
である。この図において、１は帯域通過ｐ波器、２は帯
域阻止ｐ波器、３．４はＴＴＬ変換回路、５は論理反転
回路、６は論理積回路、７は表示回路である。FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In this figure, 1 is a bandpass p-wave device, 2 is a band-elimination p-wave device, 3.4 is a TTL conversion circuit, 5 is a logic inversion circuit, 6 is an AND circuit, and 7 is a display circuit.
Claims (1)
力信号の加えられる帯域阻止ｐ波器と、前記帯域通過ｐ
波器の出力側に接続され、該帯域通過ｐ波器から得られ
る信号の有無によって“１“、または°“０゛の２値信
号を出力する第１の２値変換回路と、前記帯域阻止Ｐ波
器の出力側に接続され、該帯域阻止ｐ波器から得られる
信号の有無によって“１゛、または０゛の２値信号を出
力する第２の２値変換回路と、前記第１の２値変換回路
の出力と前記第２の２値変換回路の出力とをうけて両者
の論理をとる回路とによって構成され、該論理回路の出
力の有無により前記入力信号の検出および良否を判定す
ることを特徴とする発生信号検出装置。A bandpass p-wave device to which an input signal is applied, a band-stop p-wave device to which the input signal is also applied, and a band-pass p-wave device to which the input signal is applied.
a first binary conversion circuit that is connected to the output side of the band-pass p-wave device and outputs a binary signal of “1” or “0” depending on the presence or absence of a signal obtained from the band-pass p-wave device; a second binary conversion circuit that is connected to the output side of the P-wave device and outputs a binary signal of “1” or 0 depending on the presence or absence of a signal obtained from the band-elimination P-wave device; It is constituted by a circuit that receives the output of the binary conversion circuit and the output of the second binary conversion circuit and calculates the logic of both, and detects the input signal and determines the quality based on the presence or absence of the output of the logic circuit. A generated signal detection device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15084782U JPS5956577U (en) | 1982-10-06 | 1982-10-06 | Generated signal detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15084782U JPS5956577U (en) | 1982-10-06 | 1982-10-06 | Generated signal detection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5956577U true JPS5956577U (en) | 1984-04-13 |
Family
ID=30334451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15084782U Pending JPS5956577U (en) | 1982-10-06 | 1982-10-06 | Generated signal detection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5956577U (en) |
-
1982
- 1982-10-06 JP JP15084782U patent/JPS5956577U/en active Pending
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