JPS58101551U

JPS58101551U - Pulse signal regenerator

Info

Publication number: JPS58101551U
Application number: JP13884682U
Authority: JP
Inventors: 大島英男
Original assignee: 日本放送協会
Priority date: 1982-09-16
Filing date: 1982-09-16
Publication date: 1983-07-11
Also published as: JPS5846597Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図ａおよびｂはそれぞれ従来のＰＣＭ信号再生装置
の構成を示すフ扇ツク図およびその各回路部分における
信号波形図、第２図ａおよびｂはそれぞれ本考案パルス
信号再生装置をＰＣＭ信号再生装置に構成した場合の一
例の構成を示すブロック図お□よびその各回路部分にお
ける信号波形図、第３図ａおよびｂはそれぞれ同じく本
考案を適用したＰＣＭ信号再生装置の構成の他の例を示
すブロック図およびその各回路部分における信号波形図
である。１・・・前置増幅器、２・・・パルス判定回路、３・・
・ビット同期信号分離回路、４・・・前置増幅器、５・
・・１ビツト遅延回路、６・・・減算回路、７・・・第
１パルス−判定回路、８・・・ビット同期信号分離回路
、９・・・極性反転回路、「０・・・第２パルス判定回
路、１１・・・Ｒ３７９７１７０７１回路、１２・・・
前置増幅器、１３・・・第１サンプルホールド回路、１
４・・・第２サンプルホールド回路、１５・・・ビット
同期信号分離回路、１６・・・第１ゲート回路、１７・
・・第２ゲート回路、１８・・・フリップフロップ回路
、１９・・・第１減算回路、２０・・・第２減算回路、
２１・・・第３ゲート回路、２２・・・極性反転回路、
２３・・・第１パルス判定回路、２４・・・第２パルス
判定回路、２５・・・Ｒ３７９７１７０７１回路、Ａ・
・・第１回路部分、Ｂ・・・第２回路部分。Figures 1a and b are fan diagrams showing the configuration of a conventional PCM signal reproducing device and signal waveform diagrams in each circuit part thereof, and Figures 2a and b are respectively diagrams showing the configuration of a conventional PCM signal reproducing device. A block diagram □ showing an example of the configuration of a device, a signal waveform diagram in each circuit part, and FIGS. 3a and 3b respectively show other examples of the configuration of a PCM signal reproducing device to which the present invention is applied. FIG. 2 is a block diagram shown and signal waveform diagrams in each circuit portion thereof. 1... Preamplifier, 2... Pulse judgment circuit, 3...
・Bit synchronization signal separation circuit, 4... preamplifier, 5.
... 1-bit delay circuit, 6... Subtraction circuit, 7... First pulse-judgment circuit, 8... Bit synchronization signal separation circuit, 9... Polarity inversion circuit, "0... Second Pulse judgment circuit, 11...R379717071 circuit, 12...
Preamplifier, 13...first sample and hold circuit, 1
4... Second sample hold circuit, 15... Bit synchronization signal separation circuit, 16... First gate circuit, 17...
... second gate circuit, 18 ... flip-flop circuit, 19 ... first subtraction circuit, 20 ... second subtraction circuit,
21... Third gate circuit, 22... Polarity inversion circuit,
23...First pulse determination circuit, 24...Second pulse determination circuit, 25...R379717071 circuit, A.
...first circuit part, B...second circuit part.

Claims

[Scope of utility model registration request]

A first circuit portion that forms a level difference signal between an input pulse signal and a signal obtained by delaying the human pulse signal by one bit period, and an output signal of the first circuit portion is divided into two, and one of the two is divided into two. the other through the first level determination circuit,
The signal is supplied to the two input terminals of the set/reset flip-flop circuit through a polarity inversion circuit and a second level determination circuit, and the DC fluctuation received by the signal transmission system of the input pulse signal is output from the output terminal of the set/reset flip-flop circuit. removed, and
1. A pulse signal reproducing device comprising: a second circuit portion adapted to extract an output pulse signal whose waveform has been shaped in accordance with the sign relationship of the input pulse signal.