JPS59161197U - Buzzer circuit - Google Patents
Buzzer circuitInfo
- Publication number
- JPS59161197U JPS59161197U JP5694083U JP5694083U JPS59161197U JP S59161197 U JPS59161197 U JP S59161197U JP 5694083 U JP5694083 U JP 5694083U JP 5694083 U JP5694083 U JP 5694083U JP S59161197 U JPS59161197 U JP S59161197U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- buzzer
- input
- input signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るブザー回路が用いられる遠隔制御
システムの構成図、第２図は従来例の回路図、第３図お
よび第４図は同上の動作を示すタイムチャート、第５１
図は本考案−実施例の回路図、第６図および第７図は同
上の動作を示すタイムチ” １ ｇ’ｔ［嬬ム、２６□
、。５１、ヶ。あ、３ｆｔ−１＊ｌ＜）Ｌｙス検知回路
、４は単安定マルチ回路、６はアンド回路、７は短パル
ス検知回路、８はオア回路、９は駆動回路である。FIG. 1 is a block diagram of a remote control system using the buzzer circuit according to the present invention, FIG. 2 is a circuit diagram of a conventional example, FIGS. 3 and 4 are time charts showing the same operation, and FIG.
The figure is a circuit diagram of the present invention - an embodiment, and Figures 6 and 7 are time charts showing the operation of the above.
,. 51 months. Ah, 3ft-1*l<) Lys detection circuit, 4 is a monostable multi-circuit, 6 is an AND circuit, 7 is a short pulse detection circuit, 8 is an OR circuit, and 9 is a drive circuit.
Claims (1)
るいは連続音を発生するようにブザーを駆動して成るブ
ザー回路において、入力信号を時定数の矢きい積分回路
およびし−きい値回路よりなる長パルス検知回路と、入
力信号の立上りにてトリガされる単安定マルチ回路およ
び単安定マルチ回路出力と入力信号の反転信号を入力と
するアンド回路よりなる短パルス検知回路と、両検知回
路出力を入力とするオア回路と、オア回路出力にてブザ
ーを駆動する駆動回路とを設けたことを特徴とするブザ
ー回路。゛ In a buzzer circuit that drives a buzzer to generate a short tone or continuous tone depending on whether the input signal is a short pulse or a long pulse, the input signal is input from a time constant integrator circuit and a threshold circuit. A long pulse detection circuit consisting of a monostable multi-circuit triggered by the rising edge of an input signal and a short pulse detection circuit consisting of an AND circuit whose input is the output of the monostable multi-circuit and the inverted signal of the input signal, and the output of both detection circuits. What is claimed is: 1. A buzzer circuit comprising: an OR circuit that receives as an input, and a drive circuit that drives a buzzer using the output of the OR circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5694083U JPS59161197U (en) | 1983-04-15 | 1983-04-15 | Buzzer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5694083U JPS59161197U (en) | 1983-04-15 | 1983-04-15 | Buzzer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59161197U true JPS59161197U (en) | 1984-10-29 |
Family
ID=30187256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5694083U Pending JPS59161197U (en) | 1983-04-15 | 1983-04-15 | Buzzer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161197U (en) |
-
1983
- 1983-04-15 JP JP5694083U patent/JPS59161197U/en active Pending
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