JPS59121943U - logic level setting circuit - Google Patents
logic level setting circuitInfo
- Publication number
- JPS59121943U JPS59121943U JP1489583U JP1489583U JPS59121943U JP S59121943 U JPS59121943 U JP S59121943U JP 1489583 U JP1489583 U JP 1489583U JP 1489583 U JP1489583 U JP 1489583U JP S59121943 U JPS59121943 U JP S59121943U
- Authority
- JP
- Japan
- Prior art keywords
- logic
- circuit
- logic level
- level setting
- setting circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来におけるロジックレベル設定回路を示す回
路構成図、第２図および第３図は同回路の信号波形図、
第４図は本考案の一実施例におけるロジックレベル設定
回路を示す回路構成図である。
１．２・・・ノンスレッシュホールド（ＮＴＬ）回路、
３・・・インテグレーテッドインジエタションロジック
（Ｉ２Ｌ）回路、４・・印シックレベル設定回路、４１
・・・差動増幅器、４２・・・出力回路。Figure 1 is a circuit configuration diagram showing a conventional logic level setting circuit, Figures 2 and 3 are signal waveform diagrams of the same circuit,
FIG. 4 is a circuit configuration diagram showing a logic level setting circuit in an embodiment of the present invention. 1.2...Non-threshold (NTL) circuit,
3... Integrated injection logic (I2L) circuit, 4... Marked sick level setting circuit, 41
...Differential amplifier, 42...Output circuit.
Claims (2)
回路間に挿入され、第１のロジック回路の出力信号レベ
ルを第２のロジック回路で使用するロジックレベルに変
換するロジックレベル設定回路において、一方の差動入
力端に前記第１のロジック回路の出力信号を導入する差
動増幅器と、前記第１のロジック回路と同一構成をなし
前記差動増幅器の他方の差動入力端に基準ロジックレベ
ルを与える出力回路とを具備したことを特徴とするロジ
ックレベル設定回路。(1) A logic level setting circuit that is inserted between first and second logic circuits that are cascade-connected to each other and converts the output signal level of the first logic circuit to a logic level used in the second logic circuit, a differential amplifier which introduces the output signal of the first logic circuit into one differential input terminal; and a reference logic level signal which is connected to the other differential input terminal of the differential amplifier and which has the same configuration as the first logic circuit. A logic level setting circuit characterized by comprising an output circuit that provides.
ェクションロジック回路から構成したことを特徴とする
実用新案登録請求の範囲第１項記載のロジックレベル設
定回路。(2) The logic level setting circuit according to claim 1, wherein the second logic circuit is an inch-rated injection logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1489583U JPS59121943U (en) | 1983-02-03 | 1983-02-03 | logic level setting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1489583U JPS59121943U (en) | 1983-02-03 | 1983-02-03 | logic level setting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59121943U true JPS59121943U (en) | 1984-08-16 |
Family
ID=30146236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1489583U Pending JPS59121943U (en) | 1983-02-03 | 1983-02-03 | logic level setting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121943U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4322377Y1 (en) * | 1964-06-12 | 1968-09-19 |
-
1983
- 1983-02-03 JP JP1489583U patent/JPS59121943U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4322377Y1 (en) * | 1964-06-12 | 1968-09-19 |
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