JPS60127033U - Logic circuit output circuit - Google Patents
Logic circuit output circuitInfo
- Publication number
- JPS60127033U JPS60127033U JP1272284U JP1272284U JPS60127033U JP S60127033 U JPS60127033 U JP S60127033U JP 1272284 U JP1272284 U JP 1272284U JP 1272284 U JP1272284 U JP 1272284U JP S60127033 U JPS60127033 U JP S60127033U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reset
- output
- signal
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の分周器を構成するT型フリップフロップ
を示す図、第2図は同T型フリップフロップの動作を説
明するための信号波形図、第3図はこの考案の1実施例
を示ず分周器のブロック図、第4図は同分周器の動作を
説明するための信号波形図である。
11:T型フリップフロップ、12:インバータ、13
:論理積回路。Fig. 1 is a diagram showing a T-type flip-flop that constitutes a conventional frequency divider, Fig. 2 is a signal waveform diagram for explaining the operation of the T-type flip-flop, and Fig. 3 is an embodiment of this invention. 4 is a block diagram of the frequency divider, and FIG. 4 is a signal waveform diagram for explaining the operation of the frequency divider. 11: T-type flip-flop, 12: Inverter, 13
: AND circuit.
Claims (1)
前記リセット信号と同−論理状態のリセット出力信号を
出力する少なくとも1段のT型フリップフロップと、前
記リセット信号の論理状態を反転す名反転回路と、この
反転回路の出力と前記リセット出力信号を入力に受ける
論理積回路と゛からなり、この論理積回路より出力信号
を導出するようにした論理回路の出力回路。at least one stage T-type flip-flop that is reset upon receiving a reset signal and outputs a reset output signal having the same logic state as the reset signal in the reset state; and an inverter circuit that inverts the logic state of the reset signal. An output circuit for a logic circuit comprising an AND circuit receiving the output of the inversion circuit and the reset output signal as inputs, and an output signal is derived from the AND circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1272284U JPS60127033U (en) | 1984-01-31 | 1984-01-31 | Logic circuit output circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1272284U JPS60127033U (en) | 1984-01-31 | 1984-01-31 | Logic circuit output circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60127033U true JPS60127033U (en) | 1985-08-27 |
JPH0332115Y2 JPH0332115Y2 (en) | 1991-07-08 |
Family
ID=30496054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1272284U Granted JPS60127033U (en) | 1984-01-31 | 1984-01-31 | Logic circuit output circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60127033U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007088730A (en) * | 2005-09-21 | 2007-04-05 | Mitsubishi Electric Corp | Pulse shaping circuit |
-
1984
- 1984-01-31 JP JP1272284U patent/JPS60127033U/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007088730A (en) * | 2005-09-21 | 2007-04-05 | Mitsubishi Electric Corp | Pulse shaping circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0332115Y2 (en) | 1991-07-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS60127033U (en) | Logic circuit output circuit | |
JPS6072037U (en) | Schmitt circuit | |
JPS6020695U (en) | Input signal detection circuit | |
JPS60163837U (en) | Synchronous up-down counter circuit | |
JPS6119859U (en) | diagnostic circuit | |
JPS59144931U (en) | Latched comparator | |
JPS60158332U (en) | reset circuit | |
JPS59121943U (en) | logic level setting circuit | |
JPS5882039U (en) | phase comparison circuit | |
JPS606346U (en) | signal delay circuit | |
JPS60192199U (en) | programmable selection circuit | |
JPS58107633U (en) | Output circuit | |
JPS60139342U (en) | odd number divider circuit | |
JPS5911064U (en) | signal processing circuit | |
JPS5956845U (en) | counter circuit | |
JPS6140043U (en) | Differential A/D converter | |
JPS5837249U (en) | Momentary input transmission circuit | |
JPS59106234U (en) | Delay circuit in TTL circuit | |
JPS60120499U (en) | Variable duty ratio circuit for sound output circuit | |
JPS59189384U (en) | R, G, B signal input circuit | |
JPS6181221U (en) | ||
JPS601035U (en) | delay device | |
JPS6114520U (en) | High frequency amplifier protection circuit | |
JPS5952753U (en) | signal transmission circuit | |
JPS6039975U (en) | Rotary encoder frequency discrimination circuit |