JPS601035U

JPS601035U - delay device

Info

Publication number: JPS601035U
Application number: JP1984073441U
Authority: JP
Inventors: 福原　直之; 阪本　稔
Original assignee: 三菱電機株式会社
Priority date: 1984-05-17
Filing date: 1984-05-17
Publication date: 1985-01-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の遅延装置を示すブロック図、第２図はこ
の考案の一実施例を示すブロック図である。図において、４５．５５は集積回路、４１〜４４．５１
〜５４は反転回路、４は第１の遅延線路、５は第２の遅
延線路、６は遅延装置である。なお、図中同一符号はそれぞれ同一または相当部分を示
すものとする。FIG. 1 is a block diagram showing a conventional delay device, and FIG. 2 is a block diagram showing an embodiment of this invention. In the figure, 45.55 is an integrated circuit, 41 to 44.51
54 is an inverting circuit, 4 is a first delay line, 5 is a second delay line, and 6 is a delay device. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

a first delay circuit in which half of the logic circuits of a first integrated circuit having an even number of logic circuits and half of the logic circuits of a second integrated circuit having an even number of logic circuits are disposed;
A delay device comprising: a second delay circuit in which the other half of the logic circuits of the first integrated circuit and the other half of the logic circuits of the second integrated circuit are disposed.