JPS6045519U - Digital stretch clip circuit - Google Patents

Digital stretch clip circuit

Info

Publication number
JPS6045519U
JPS6045519U JP13854683U JP13854683U JPS6045519U JP S6045519 U JPS6045519 U JP S6045519U JP 13854683 U JP13854683 U JP 13854683U JP 13854683 U JP13854683 U JP 13854683U JP S6045519 U JPS6045519 U JP S6045519U
Authority
JP
Japan
Prior art keywords
digital
signal
clipping
slice
stretch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13854683U
Other languages
Japanese (ja)
Other versions
JPH0224262Y2 (en
Inventor
延孝 篠原
南 昭彦
平川 秀治
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP13854683U priority Critical patent/JPS6045519U/en
Publication of JPS6045519U publication Critical patent/JPS6045519U/en
Application granted granted Critical
Publication of JPH0224262Y2 publication Critical patent/JPH0224262Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Picture Signal Circuits (AREA)
  • Processing Of Color Television Signals (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案のディジタル・ストレッチ・クリップ
回路の一実施例の構成を示すブロック図、第2図は同上
ディジタル・ストレッチ・クリップ回路におけるストレ
ッチ回路の詳細な構成を示すブロック図、第3図は同上
ディジタル・ストレッチ・クリップ回路における入力対
出力の関係を示す図である。
FIG. 1 is a block diagram showing the configuration of one embodiment of the digital stretch clip circuit of this invention, FIG. 2 is a block diagram showing the detailed configuration of the stretch circuit in the digital stretch clip circuit of the same invention, and FIG. 3 FIG. 2 is a diagram showing the input-to-output relationship in the digital stretch clip circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のビット長からなるディジタル信号に対して、上限
と下限の二つのスライス・レベルを設定し、スライスφ
レベル間にあるディジタル信号を任意の最小値と最大値
の間にストレッチする拡大率を求め、信号をストレッチ
する第1の手段と、下限のスライス・レベル以下の信号
を上記の最小値でクリップする第2の手段と、上限のス
ライス・レベル以上の信号を上記の最大値でクリップす
る第3の手段とを具備してなるディジタル・ストレッチ
拳クリップ回路。
Two slice levels, an upper limit and a lower limit, are set for a digital signal consisting of multiple bit lengths, and the slice φ
The first means of stretching the signal by determining the expansion ratio for stretching the digital signal between the levels between the arbitrary minimum and maximum values, and clipping the signal below the lower limit slice level at the above minimum value. A digital stretch fist clipping circuit comprising a second means and a third means for clipping a signal above the upper limit slice level at the maximum value.
JP13854683U 1983-09-07 1983-09-07 Digital stretch clip circuit Granted JPS6045519U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13854683U JPS6045519U (en) 1983-09-07 1983-09-07 Digital stretch clip circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13854683U JPS6045519U (en) 1983-09-07 1983-09-07 Digital stretch clip circuit

Publications (2)

Publication Number Publication Date
JPS6045519U true JPS6045519U (en) 1985-03-30
JPH0224262Y2 JPH0224262Y2 (en) 1990-07-03

Family

ID=30310829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13854683U Granted JPS6045519U (en) 1983-09-07 1983-09-07 Digital stretch clip circuit

Country Status (1)

Country Link
JP (1) JPS6045519U (en)

Also Published As

Publication number Publication date
JPH0224262Y2 (en) 1990-07-03

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