JPS5827777U - Delay time measurement circuit - Google Patents
Delay time measurement circuitInfo
- Publication number
- JPS5827777U JPS5827777U JP12211181U JP12211181U JPS5827777U JP S5827777 U JPS5827777 U JP S5827777U JP 12211181 U JP12211181 U JP 12211181U JP 12211181 U JP12211181 U JP 12211181U JP S5827777 U JPS5827777 U JP S5827777U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- delay time
- output
- gate
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005259 measurement Methods 0.000 title 1
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来回路の一例、第２図は第１図の各部波形例
、第３図はこの考案による実施例回路、第４図は第３図
の各部波形例。゛
１・・・・・七号Ａの接続端子、２・・・・・・信号Ｂ
の接続端子、３・・・・・・クロック信号の接続端子、
４・・曲排他的論理和回路、５・・・・・・ゲート、６
・・・・・・カウンタ、７・・・・・・Ｄ型フリップフ
ロップ、８・・・・・・ゲート。FIG. 1 is an example of a conventional circuit, FIG. 2 is an example of waveforms of various parts of FIG. 1, FIG. 3 is an example circuit according to this invention, and FIG. 4 is an example of waveforms of various parts of FIG. 3.゛1... Connection terminal of No. 7 A, 2... Signal B
connection terminal, 3...connection terminal for clock signal,
4... Song exclusive OR circuit, 5... Gate, 6
...Counter, 7...D type flip-flop, 8...Gate.
Claims (1)
る第１のゲートと、 この第１のゲート出力を入力とするカウンタとをもつ信
号Ａと信号Ｂの遅延時間測定回路において、 信号Ａと信号ＢをそれぞれＤ端子、Ｔ端子に接続するＤ
型フリップ７０ツブと、 信号Ａと信号Ｂを入力とし、その出力を前記フリップフ
ロップのＲ端子に接続する第２のゲートとを設け、 信号Ａまたは信号Ｂのどちらかの信号がオンのときはフ
リップフロップ７のリセットを解除するように第２のゲ
ート出力を設定し、 前記フリップフロップの出力と信号Ａを前記排他的論理
和回路の入力とすることを特徴とする遅延時間測定回路
。[Claims for Utility Model Registration] An exclusive OR circuit that receives signals A and B as inputs, a first gate that receives the output of this exclusive OR circuit and a clock signal, and this first gate. In a delay time measuring circuit for signals A and B that has a counter whose output is an input, D is used to connect signal A and signal B to terminals D and T, respectively.
A 70-type flip-flop and a second gate that receives signals A and B as inputs and connects its output to the R terminal of the flip-flop are provided, and when either signal A or signal B is on, A delay time measuring circuit characterized in that a second gate output is set to release the reset of the flip-flop 7, and the output of the flip-flop and signal A are input to the exclusive OR circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12211181U JPS5827777U (en) | 1981-08-18 | 1981-08-18 | Delay time measurement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12211181U JPS5827777U (en) | 1981-08-18 | 1981-08-18 | Delay time measurement circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5827777U true JPS5827777U (en) | 1983-02-22 |
| JPS6225750Y2 JPS6225750Y2 (en) | 1987-07-01 |
Family
ID=29916043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12211181U Granted JPS5827777U (en) | 1981-08-18 | 1981-08-18 | Delay time measurement circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827777U (en) |
-
1981
- 1981-08-18 JP JP12211181U patent/JPS5827777U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6225750Y2 (en) | 1987-07-01 |
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