JPS58173949U - Burst signal receiving circuit - Google Patents
Burst signal receiving circuitInfo
- Publication number
- JPS58173949U JPS58173949U JP7221482U JP7221482U JPS58173949U JP S58173949 U JPS58173949 U JP S58173949U JP 7221482 U JP7221482 U JP 7221482U JP 7221482 U JP7221482 U JP 7221482U JP S58173949 U JPS58173949 U JP S58173949U
- Authority
- JP
- Japan
- Prior art keywords
- burst signal
- receiving circuit
- signal receiving
- matched filter
- reception timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の説明に供するもので、第１図は従来のバ
ースト信号受信回路の一例を示すブロック図、第２図は
本考案のバースト信号受信回路の一実施例を示すブロッ
ク図、第３図は第２図の回路における動作波形−である
。
１０・・・マツチドフィルタ、１１・・・微分回路、１
２．１３・・・比較器（ＧＯＭＰ）、１４・・・アンド
ゲート。The drawings are for explaining the present invention, and FIG. 1 is a block diagram showing an example of a conventional burst signal receiving circuit, FIG. 2 is a block diagram showing an embodiment of the burst signal receiving circuit of the present invention, and FIG. The diagram shows operating waveforms in the circuit of FIG. 2. 10...Matched filter, 11...Differential circuit, 1
2.13... Comparator (GOMP), 14... AND gate.
Claims (1)
出するバースト信号受信回路において、基準のバースト
信号波形に整合したマツチドフィルタと、該マツチドフ
ィルタの出力パルスの最大点をバースト信号の受信タイ
ミングとして取り出す手段とを備えたことを特徴とする
バースト信号受信回路。In a burst signal receiving circuit that detects the reception timing of a burst signal included in an input signal, a matched filter that matches the reference burst signal waveform and the maximum point of the output pulse of the matched filter are extracted as the burst signal reception timing. A burst signal receiving circuit comprising: means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7221482U JPS58173949U (en) | 1982-05-18 | 1982-05-18 | Burst signal receiving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7221482U JPS58173949U (en) | 1982-05-18 | 1982-05-18 | Burst signal receiving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58173949U true JPS58173949U (en) | 1983-11-21 |
Family
ID=30081787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7221482U Pending JPS58173949U (en) | 1982-05-18 | 1982-05-18 | Burst signal receiving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58173949U (en) |
-
1982
- 1982-05-18 JP JP7221482U patent/JPS58173949U/en active Pending
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