JPS5883863U - Synchronous signal separation circuit - Google Patents
Synchronous signal separation circuitInfo
- Publication number
- JPS5883863U JPS5883863U JP17777281U JP17777281U JPS5883863U JP S5883863 U JPS5883863 U JP S5883863U JP 17777281 U JP17777281 U JP 17777281U JP 17777281 U JP17777281 U JP 17777281U JP S5883863 U JPS5883863 U JP S5883863U
- Authority
- JP
- Japan
- Prior art keywords
- signal separation
- separation circuit
- circuit
- pedestal level
- synchronization signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は同期信号を含むビデオ信号の波形図、第２図は
ペデスタルレベルクランプによる同期信号分離回路のブ
ロック図、第３８．ｂはこの考案の同期信号分離回路の
ブロック図、及び各ブロックの波形図を示す。
図中、１０は第１の周期信号分離回路、２０はペデスタ
ルレベルクランプ回路、３０は第２の同期信号分離回路
、４１はサンプルパルス発生回路、４２はゲートパルス
発生回路を示す。1 is a waveform diagram of a video signal including a sync signal, FIG. 2 is a block diagram of a sync signal separation circuit using a pedestal level clamp, and 38. b shows a block diagram of the synchronization signal separation circuit of this invention and a waveform diagram of each block. In the figure, 10 is a first periodic signal separation circuit, 20 is a pedestal level clamp circuit, 30 is a second synchronization signal separation circuit, 41 is a sample pulse generation circuit, and 42 is a gate pulse generation circuit.
Claims (1)
と、前記第１の同期信号分離回路の出力で形成されたサ
ンプリングパルスによって制御されるペデスタルレベル
クランプ回路と、前記ペデスタルレベルクランプ回路の
出力から同期信号を抽出する第２の同期信号分離回路よ
り成り、前記第１の同期信号分離回路、及び前記ペデス
タルレベルクランプ回路に使用されている第１のローパ
スフィルタより高いカットオフ周波数を持った第２のロ
ーパスフィルタを、前記第２の周期信号分離回路に使用
したことを特徴とする同期信号分離回路。a first sync signal separation circuit that detects the sync chip level; a pedestal level clamp circuit that is controlled by a sampling pulse formed by the output of the first sync signal separation circuit; and a pedestal level clamp circuit that detects synchronization from the output of the pedestal level clamp circuit. a second synchronization signal separation circuit for extracting a signal, the second synchronization signal separation circuit having a higher cutoff frequency than the first low-pass filter used in the first synchronization signal separation circuit and the pedestal level clamp circuit; A synchronization signal separation circuit characterized in that a low-pass filter is used in the second periodic signal separation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17777281U JPS5883863U (en) | 1981-12-01 | 1981-12-01 | Synchronous signal separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17777281U JPS5883863U (en) | 1981-12-01 | 1981-12-01 | Synchronous signal separation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5883863U true JPS5883863U (en) | 1983-06-07 |
Family
ID=29971960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17777281U Pending JPS5883863U (en) | 1981-12-01 | 1981-12-01 | Synchronous signal separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5883863U (en) |
-
1981
- 1981-12-01 JP JP17777281U patent/JPS5883863U/en active Pending
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