JPS6047374U - interface circuit - Google Patents
interface circuitInfo
- Publication number
- JPS6047374U JPS6047374U JP13974483U JP13974483U JPS6047374U JP S6047374 U JPS6047374 U JP S6047374U JP 13974483 U JP13974483 U JP 13974483U JP 13974483 U JP13974483 U JP 13974483U JP S6047374 U JPS6047374 U JP S6047374U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- section
- video signal
- sample value
- interface circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のインターフェイス回路のブロック図、第
２図は第１図におけるビデオ信号の波形図、第３図はこ
の考案のインターフェイ−ス回路の１実施例のブロック
図である。
３・・・同期信号分離部、６・・・サンプリング部、８
・・・Ａ／Ｄ変換部、９・・・ピークホールド部、１ｏ
・・・基準信号発生部。FIG. 1 is a block diagram of a conventional interface circuit, FIG. 2 is a waveform diagram of the video signal in FIG. 1, and FIG. 3 is a block diagram of an embodiment of the interface circuit of the present invention. 3... Synchronization signal separation section, 6... Sampling section, 8
... A/D conversion section, 9... Peak hold section, 1o
...Reference signal generation section.
Claims (1)
直同期信号を取り出し分離して出力する同期信号分離部
と、前記ビデオ信号に含まれる映像信号をサンプリング
してサンプル値を保持しサンプル値信号を出力するサン
プリング部と、前記分離部からの水平同期信号のピーク
値を所定時間ごとに保持するピークホールド部と、該ホ
ールド部により保持された前記ピーク値に応じたレベル
の基準信号を出力する基準信号発生部と、前記基準信号
と前記サンプル値信号との差にもとづくデジタルデータ
信号を出力するアナログ−デジタル変換部とを備えたイ
ンターフェイス回路。A synchronization signal separation section extracts, separates, and outputs horizontal and vertical synchronization signals included in the video signal from the video signal generation section; and a synchronization signal separation section that samples the video signal included in the video signal, holds the sample value, and generates a sample value signal. a sampling section for outputting; a peak hold section for holding the peak value of the horizontal synchronizing signal from the separation section at predetermined time intervals; and a reference for outputting a reference signal at a level corresponding to the peak value held by the hold section. An interface circuit comprising: a signal generator; and an analog-to-digital converter that outputs a digital data signal based on a difference between the reference signal and the sample value signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13974483U JPS6047374U (en) | 1983-09-08 | 1983-09-08 | interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13974483U JPS6047374U (en) | 1983-09-08 | 1983-09-08 | interface circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6047374U true JPS6047374U (en) | 1985-04-03 |
Family
ID=30313115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13974483U Pending JPS6047374U (en) | 1983-09-08 | 1983-09-08 | interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6047374U (en) |
-
1983
- 1983-09-08 JP JP13974483U patent/JPS6047374U/en active Pending
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