JPS5828467U - synchronous circuit - Google Patents
synchronous circuitInfo
- Publication number
- JPS5828467U JPS5828467U JP12290381U JP12290381U JPS5828467U JP S5828467 U JPS5828467 U JP S5828467U JP 12290381 U JP12290381 U JP 12290381U JP 12290381 U JP12290381 U JP 12290381U JP S5828467 U JPS5828467 U JP S5828467U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization
- synchronizes
- signal
- synchronization signal
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は同期回路の従来例の構成を示すブロック図、第
２図は第１図の従来例の動作を説明するための各部の波
形を示す波形図、第３図は本考案の同期回路の構成を示
すブロック図、第４図は本考案の動作を説明するための
各部の波形を示す波形図である。
２・・・垂直同期分離回路、３・・・カウンタ回路、４
・・・水平同期分離回路、７・・・クロック発生回路、
８゜１４・・・ＲＯＭ回路、１１・・・水平パルス判定
回路、１３・・・カウンタ。Fig. 1 is a block diagram showing the configuration of a conventional example of a synchronous circuit, Fig. 2 is a waveform diagram showing waveforms of various parts to explain the operation of the conventional example of Fig. 1, and Fig. 3 is a synchronous circuit of the present invention. FIG. 4 is a waveform diagram showing waveforms of various parts to explain the operation of the present invention. 2... Vertical synchronization separation circuit, 3... Counter circuit, 4
...Horizontal synchronization separation circuit, 7...Clock generation circuit,
8゜14...ROM circuit, 11...Horizontal pulse determination circuit, 13...Counter.
Claims (1)
信号と同期をとり、各種の処理を行う基準となる信号を
出力する同期回路において、ビデオ信号の垂直同期信号
と同期を取り、所定の期間水平同期信号抜き取り用パル
スを出力する手段と、この抜き取り用パルス期間におけ
る同期信号が設定された許容時間幅であるかを判定する
手段と、その判定された結果に基づいてその同期信号と
同期してカウンタを動作させる手段とを具備して構成さ
れることを特徴とする同期回路。In a synchronization circuit that captures a video signal, synchronizes it with the vertical and horizontal synchronization signals of the video signal, and outputs a reference signal for various processing, it synchronizes with the vertical synchronization signal of the video signal and synchronizes the horizontal means for outputting a synchronization signal extraction pulse; means for determining whether the synchronization signal during this extraction pulse period is within a set allowable time width; and means for synchronizing with the synchronization signal based on the determined result. A synchronous circuit comprising means for operating a counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12290381U JPS5828467U (en) | 1981-08-19 | 1981-08-19 | synchronous circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12290381U JPS5828467U (en) | 1981-08-19 | 1981-08-19 | synchronous circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5828467U true JPS5828467U (en) | 1983-02-24 |
Family
ID=29916816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12290381U Pending JPS5828467U (en) | 1981-08-19 | 1981-08-19 | synchronous circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5828467U (en) |
-
1981
- 1981-08-19 JP JP12290381U patent/JPS5828467U/en active Pending
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