JPS59152866U - Composite synchronization signal frequency divider circuit - Google Patents

Composite synchronization signal frequency divider circuit

Info

Publication number
JPS59152866U
JPS59152866U JP4713983U JP4713983U JPS59152866U JP S59152866 U JPS59152866 U JP S59152866U JP 4713983 U JP4713983 U JP 4713983U JP 4713983 U JP4713983 U JP 4713983U JP S59152866 U JPS59152866 U JP S59152866U
Authority
JP
Japan
Prior art keywords
synchronization signal
circuit
composite synchronization
flip
frequency divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4713983U
Other languages
Japanese (ja)
Other versions
JPH018059Y2 (en
Inventor
邦夫 米野
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP4713983U priority Critical patent/JPS59152866U/en
Publication of JPS59152866U publication Critical patent/JPS59152866U/en
Application granted granted Critical
Publication of JPH018059Y2 publication Critical patent/JPH018059Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図AないしJは、夫々複合同期信号とその波形変換
によって得られる各種信号の信号波形図、゛第2図は、
従来の水平同期信号の分周回路の一例を示す回路構成図
、第3図は、本考案の複合同期信号の分周回路の一実施
例を示す回路構成図、第4図はその要部回路図である。 2・・・・・・微分回路、3・・・・・・フリップフロ
ップ回路、3t・・・・・・トリガ入力端子、3r・・
・・・・リセット入力端子、4・・・・・・微分回路、
11・・・・・・分周回路、12・・・・・・補正回路
、13・・・・・・積分回路、14・・・・・・微分回
路。
1A to 1J are signal waveform diagrams of the composite synchronization signal and various signals obtained by its waveform conversion, respectively.
FIG. 3 is a circuit diagram showing an example of a conventional frequency dividing circuit for a horizontal synchronizing signal. FIG. 3 is a circuit diagram showing an example of a frequency dividing circuit for a composite synchronizing signal of the present invention. FIG. It is a diagram. 2...Differential circuit, 3...Flip-flop circuit, 3t...Trigger input terminal, 3r...
...Reset input terminal, 4... Differential circuit,
11... Frequency dividing circuit, 12... Correction circuit, 13... Integrating circuit, 14... Differentiating circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 水平同期信号に対し垂直同期信号の極性反転信号が排他
的論理和として重畳した複合同期信号が供給され、該複
合同期信号を微分する微分回路と、該微分回路の微分出
力のうち正極性又は負極性のいずれか一方の微分出力に
よってトリガされるトリガ型のフリップフロップ回路と
、該フリップフロップ回路の出力を微分して前記微分出
力の了の周波数の分周出力を得る微分回路と、前記複合
同期信号に含まれる垂直同期信号の前縁部を検出し、検
出時点で前記フリップフロップ回路をリセットし、該フ
リップフロップ回路のトリガタイミングのずれを補正す
る補正回路とから構成してなる複合同期信号の分周回路
A composite synchronization signal in which a polarity inverted signal of a vertical synchronization signal is superimposed on a horizontal synchronization signal as an exclusive OR is supplied, and a differentiation circuit that differentiates the composite synchronization signal and a positive or negative polarity of the differential output of the differentiation circuit are supplied. a trigger-type flip-flop circuit that is triggered by a differential output of either one of the differential outputs; a differentiation circuit that differentiates the output of the flip-flop circuit to obtain a frequency-divided output of the frequency of the differential output; and the composite synchronization circuit. A composite synchronization signal comprising a correction circuit that detects a leading edge of a vertical synchronization signal included in the signal, resets the flip-flop circuit at the time of detection, and corrects a shift in trigger timing of the flip-flop circuit. Frequency divider circuit.
JP4713983U 1983-03-30 1983-03-30 Composite synchronization signal frequency divider circuit Granted JPS59152866U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4713983U JPS59152866U (en) 1983-03-30 1983-03-30 Composite synchronization signal frequency divider circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4713983U JPS59152866U (en) 1983-03-30 1983-03-30 Composite synchronization signal frequency divider circuit

Publications (2)

Publication Number Publication Date
JPS59152866U true JPS59152866U (en) 1984-10-13
JPH018059Y2 JPH018059Y2 (en) 1989-03-02

Family

ID=30177690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4713983U Granted JPS59152866U (en) 1983-03-30 1983-03-30 Composite synchronization signal frequency divider circuit

Country Status (1)

Country Link
JP (1) JPS59152866U (en)

Also Published As

Publication number Publication date
JPH018059Y2 (en) 1989-03-02

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