JPS6040164U - Display clock generation circuit - Google Patents
Display clock generation circuitInfo
- Publication number
- JPS6040164U JPS6040164U JP13236883U JP13236883U JPS6040164U JP S6040164 U JPS6040164 U JP S6040164U JP 13236883 U JP13236883 U JP 13236883U JP 13236883 U JP13236883 U JP 13236883U JP S6040164 U JPS6040164 U JP S6040164U
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- synchronization signal
- circuit
- display clock
- clock generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の表示クロック発生回路によりスーパーイ
ンポーズを行なうようにしたＣＲＴディスプレー装置の
構成を示すブロック図である。第２図は従来の表示クロ
ック発生回路の動作を示すタイムチャートである。第３
図は本考案に係る表示クロック発生回路の一実施例を示
す回路構成図である。第４図はこの実施例の動作を示す
タイムチャートである。
１１・・・・・・外部ビデオ信号入力端子、１２・・・
・・・同期分離回路、１４・・・・・・Ｒ−Ｓフリップ
フロップ、１７・・・・・・表示クロック出力端子、２
０・・・・・・発振回路、２１・・・・・・発振回路の
制御入力端子。FIG. 1 is a block diagram showing the configuration of a CRT display device in which superimposition is performed using a conventional display clock generation circuit. FIG. 2 is a time chart showing the operation of a conventional display clock generation circuit. Third
The figure is a circuit configuration diagram showing an embodiment of a display clock generation circuit according to the present invention. FIG. 4 is a time chart showing the operation of this embodiment. 11... External video signal input terminal, 12...
...Synchronization separation circuit, 14...R-S flip-flop, 17...Display clock output terminal, 2
0...Oscillation circuit, 21...Control input terminal of the oscillation circuit.
Claims (1)
よる発振出力として得られる表示クロックに基いて形成
される内部同期信号および外部からの外部同期信号が供
給され、上記内部同期信号に同期したタイミングで上記
発振回路の発振動作を停止させ上記外部同期信号に同期
したタイミングで上記発振回路の発振動作を再開させる
発振停止制御回路とを備え、上記発振回路の発振位相を
上記外部同期信号に合せるようにしたしたことを特徴と
する表示クロック発生回路。An oscillation circuit whose oscillation operation can be stopped is supplied with an internal synchronization signal formed based on a display clock obtained as an oscillation output from this oscillation circuit and an external synchronization signal from the outside, and a timing synchronized with the internal synchronization signal. and an oscillation stop control circuit that stops the oscillation operation of the oscillation circuit and restarts the oscillation operation of the oscillation circuit at a timing synchronized with the external synchronization signal, and adjusts the oscillation phase of the oscillation circuit to the external synchronization signal. A display clock generation circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13236883U JPS6040164U (en) | 1983-08-27 | 1983-08-27 | Display clock generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13236883U JPS6040164U (en) | 1983-08-27 | 1983-08-27 | Display clock generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6040164U true JPS6040164U (en) | 1985-03-20 |
Family
ID=30298935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13236883U Pending JPS6040164U (en) | 1983-08-27 | 1983-08-27 | Display clock generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6040164U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62180679A (en) * | 1986-02-04 | 1987-08-07 | Matsushita Electric Ind Co Ltd | Clock generation circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57199370A (en) * | 1981-06-03 | 1982-12-07 | Hitachi Ltd | Synchronizing signal resetting circuit of video camera |
| JPS5892172A (en) * | 1981-11-28 | 1983-06-01 | Nippon Gakki Seizo Kk | Synchronizing circuit |
-
1983
- 1983-08-27 JP JP13236883U patent/JPS6040164U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57199370A (en) * | 1981-06-03 | 1982-12-07 | Hitachi Ltd | Synchronizing signal resetting circuit of video camera |
| JPS5892172A (en) * | 1981-11-28 | 1983-06-01 | Nippon Gakki Seizo Kk | Synchronizing circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62180679A (en) * | 1986-02-04 | 1987-08-07 | Matsushita Electric Ind Co Ltd | Clock generation circuit |
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