JPS6043081U - Synchronous signal compensation circuit - Google Patents
Synchronous signal compensation circuitInfo
- Publication number
- JPS6043081U JPS6043081U JP13516183U JP13516183U JPS6043081U JP S6043081 U JPS6043081 U JP S6043081U JP 13516183 U JP13516183 U JP 13516183U JP 13516183 U JP13516183 U JP 13516183U JP S6043081 U JPS6043081 U JP S6043081U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- monostable multi
- compensation circuit
- synchronous signal
- signal compensation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の回路ブロック図、第２図は第１図にお
ける波形図である。第３図は本考案の＝実施例の回路ブ
ロック図、第４図は第３図における波形図、第５図は第
２の実施例の回路ブロック図、第６図は第５図における
波形図である。
主な図番の説明、１３・・・擬似同期信号発生回路、１
４・・・第１単安定マルチ、１６・・・ゲート回路、１
９・・・第２単安定マルチ。FIG. 1 is a circuit block diagram of a conventional example, and FIG. 2 is a waveform diagram in FIG. 1. Fig. 3 is a circuit block diagram of the embodiment of the present invention, Fig. 4 is a waveform diagram in Fig. 3, Fig. 5 is a circuit block diagram of the second embodiment, and Fig. 6 is a waveform diagram in Fig. 5. It is. Explanation of main figure numbers, 13...Pseudo synchronous signal generation circuit, 1
4...First monostable multi, 16...Gate circuit, 1
9...Second monostable multi.
Claims (1)
可能な擬似同期信号発生回路と、擬似同期信号によりト
リガされる第１の単安定マルチと、該第１単安定マルチ
出力をゲート信号として垂直同期信号を入力とするゲー
ト回路と、該ゲート回路出力蓋しくは前記第１単安定マ
ルチ出力によってトリガされる第２単安定マルチとを備
え、゛ 該第２単安定マルチ出力で前記擬似同期信号発
生回路をリセットすることを特徴とする同期信号補償回
路。A pseudo synchronization signal generation circuit whose free-running period is slightly shorter than the vertical synchronization signal period and can be reset, a first monostable multi triggered by the pseudo synchronization signal, and a vertical synchronization signal generator using the first monostable multi output as a gate signal. comprising a gate circuit receiving a synchronization signal as an input, and a second monostable multi triggered by the output lid of the gate circuit or the first monostable multi output; A synchronous signal compensation circuit characterized by resetting a generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13516183U JPS6043081U (en) | 1983-08-30 | 1983-08-30 | Synchronous signal compensation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13516183U JPS6043081U (en) | 1983-08-30 | 1983-08-30 | Synchronous signal compensation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6043081U true JPS6043081U (en) | 1985-03-26 |
| JPS643261Y2 JPS643261Y2 (en) | 1989-01-27 |
Family
ID=30304311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13516183U Granted JPS6043081U (en) | 1983-08-30 | 1983-08-30 | Synchronous signal compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043081U (en) |
-
1983
- 1983-08-30 JP JP13516183U patent/JPS6043081U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS643261Y2 (en) | 1989-01-27 |
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