JPS59164382U - control monitoring system - Google Patents
control monitoring systemInfo
- Publication number
- JPS59164382U JPS59164382U JP5694183U JP5694183U JPS59164382U JP S59164382 U JPS59164382 U JP S59164382U JP 5694183 U JP5694183 U JP 5694183U JP 5694183 U JP5694183 U JP 5694183U JP S59164382 U JPS59164382 U JP S59164382U
- Authority
- JP
- Japan
- Prior art keywords
- control
- monitoring system
- control monitoring
- terminal device
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Selective Calling Equipment (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は制御監視システムの基本ブロック回路図、第２
図は同上の制御信号波形図、第３図ａ。
ｂは同上の通常の動作タイムチャート、第４図ａ。
ｂは同上の制御信号が休止する場合の動作タイムチャー
ト、第５図は本考案の一実施例のブロック回路図である
。
１・・・・・・親機、２・・・・・・端末器、４・・・
・・・カウンタ、５・・・・・・データ出力回路。Figure 1 is the basic block circuit diagram of the control and monitoring system, Figure 2
The figure is a control signal waveform diagram same as above, and FIG. 3a. b is the normal operation time chart of the same as above, and Fig. 4a. b is an operation time chart when the same control signal as above is stopped, and FIG. 5 is a block circuit diagram of an embodiment of the present invention. 1... Base device, 2... Terminal device, 4...
...Counter, 5...Data output circuit.
Claims (1)
御する如くした制御監視システムにおいて、端末器内部
のクロックをカウントし且つ制御出力タイミング信号で
リセット声れるカウンタを端末器に設け、前記カウンタ
の出力信号又は制御出力タイミング信号によりデータ出
力回路を動作させてリレーを制御する如くして成る制御
監視システム。In a control monitoring system in which a relay provided in a terminal device is controlled by a control signal from a base device, a counter is provided in the terminal device that counts the internal clock of the terminal device and can be reset by a control output timing signal. A control monitoring system that operates a data output circuit using an output signal or a control output timing signal to control a relay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5694183U JPS59164382U (en) | 1983-04-15 | 1983-04-15 | control monitoring system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5694183U JPS59164382U (en) | 1983-04-15 | 1983-04-15 | control monitoring system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59164382U true JPS59164382U (en) | 1984-11-05 |
| JPH0129892Y2 JPH0129892Y2 (en) | 1989-09-12 |
Family
ID=30187257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5694183U Granted JPS59164382U (en) | 1983-04-15 | 1983-04-15 | control monitoring system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59164382U (en) |
-
1983
- 1983-04-15 JP JP5694183U patent/JPS59164382U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0129892Y2 (en) | 1989-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59164382U (en) | control monitoring system | |
| JPS5920732U (en) | timer circuit | |
| JPS5885867U (en) | automatic display output device | |
| JPS60102690U (en) | Radiation measuring instrument noise prevention circuit | |
| JPS6117891U (en) | Inverter control device | |
| JPS5886598U (en) | timer time setting device | |
| JPS615066U (en) | Video display device | |
| JPS60170834U (en) | Reset circuit for microcomputer | |
| JPS5828342U (en) | Fault indicator | |
| JPS5922570U (en) | telephone footing circuit | |
| JPS614233U (en) | Image memory access device | |
| JPS60116527U (en) | timer | |
| JPS58101232U (en) | microcomputer | |
| JPS5872798U (en) | PROM writing confirmation device | |
| JPS60180035U (en) | Electronics | |
| JPS59118007U (en) | Output circuit | |
| JPS591141U (en) | Tape running display circuit | |
| JPS613588U (en) | counter circuit | |
| JPS58129197U (en) | electronic clock | |
| JPS6043081U (en) | Synchronous signal compensation circuit | |
| JPS59118036U (en) | data input circuit | |
| JPS5837252U (en) | pulse width modulation circuit | |
| JPS59113815U (en) | Automatic power factor adjustment device | |
| JPS6032833U (en) | receiving device | |
| JPS60124175U (en) | Main clock device of electronic exchange |