JPS615066U - Video display device - Google Patents

Video display device

Info

Publication number
JPS615066U
JPS615066U JP8931684U JP8931684U JPS615066U JP S615066 U JPS615066 U JP S615066U JP 8931684 U JP8931684 U JP 8931684U JP 8931684 U JP8931684 U JP 8931684U JP S615066 U JPS615066 U JP S615066U
Authority
JP
Japan
Prior art keywords
display device
video display
operation mode
period
synchronization signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8931684U
Other languages
Japanese (ja)
Inventor
悟 前田
昌之 安村
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP8931684U priority Critical patent/JPS615066U/en
Publication of JPS615066U publication Critical patent/JPS615066U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一例の構成図、第２図は他の例の構成
図である。 １１はカウンタ、１２，１３はデコーダ、１４，１５−
はフリツプフロツプ、１６はアンド回路、１７はタイマ
ー回路である。FIG. 1 is a block diagram of one example of the present invention, and FIG. 2 is a block diagram of another example. 11 is a counter, 12 and 13 are decoders, 14, 15-
1 is a flip-flop, 16 is an AND circuit, and 17 is a timer circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同期信号の周期を検出し、この検出された周期の範囲に
よって動作モードの切換を行うと共に、′ タイマー回
路を設け、所定時間上記同期信号の供給が無いときには
所定の上記動作モードに切換られるよ、うにしたことを
特徴とする映像表示装置。The period of the synchronization signal is detected, and the operation mode is switched according to the range of the detected period, and a timer circuit is provided, so that when the synchronization signal is not supplied for a predetermined period of time, the operation mode is switched to the predetermined operation mode. An image display device characterized by:
JP8931684U 1984-06-15 1984-06-15 Video display device Pending JPS615066U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8931684U JPS615066U (en) 1984-06-15 1984-06-15 Video display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8931684U JPS615066U (en) 1984-06-15 1984-06-15 Video display device

Publications (1)

Publication Number Publication Date
JPS615066U true JPS615066U (en) 1986-01-13

Family

ID=30643272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8931684U Pending JPS615066U (en) 1984-06-15 1984-06-15 Video display device

Country Status (1)

Country Link
JP (1) JPS615066U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62259132A (en) * 1986-05-02 1987-11-11 Nec Corp Controller for shared crt display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62259132A (en) * 1986-05-02 1987-11-11 Nec Corp Controller for shared crt display

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