JPS6117891U - Inverter control device - Google Patents
Inverter control deviceInfo
- Publication number
- JPS6117891U JPS6117891U JP10121884U JP10121884U JPS6117891U JP S6117891 U JPS6117891 U JP S6117891U JP 10121884 U JP10121884 U JP 10121884U JP 10121884 U JP10121884 U JP 10121884U JP S6117891 U JPS6117891 U JP S6117891U
- Authority
- JP
- Japan
- Prior art keywords
- timer means
- control device
- inverter control
- drive signal
- lower arm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Protection Of Static Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例を示す回路図、第２図は第
１図の回路の要部の波形図、第３図は従来の制御回路の
一例を示す図、第４図は第３図の回路の波形図である。
１２・・・・・・入力信号発生器、１５．１６・・・・
・・タイマ、１７・・・・・・フリツプフロップ。Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a waveform diagram of the main parts of the circuit shown in Fig. 1, Fig. 3 is a diagram showing an example of a conventional control circuit, and Fig. 4 is a diagram showing an example of a conventional control circuit. FIG. 4 is a waveform diagram of the circuit of FIG. 3; 12... Input signal generator, 15.16...
...Timer, 17...Flip-flop.
Claims (1)
イマ手段と、第１のタイマ手段の出力で計時を開始する
とともに上アーム駆動信号を出力し、かつ設定時間後上
記駆動信号を停止する第２のタイマ手段と、第１のタイ
マ手段の駆動と同時にリセットされ、かつ第２のタイマ
手段の計時完了後一定時間後にセットされ下アーム駆動
信号を出力する手段とを備えたことを特徴とするインバ
ータの制御装置。a first timer means for starting time measurement in response to a common upper and lower arm signal; and a first timer means for starting time measurement by the output of the first timer means, outputting an upper arm drive signal, and stopping the drive signal after a set time. The present invention is characterized by comprising a second timer means, and a means that is reset at the same time as the first timer means is driven, and is set after a certain period of time after the second timer means completes timing, and outputs a lower arm drive signal. Inverter control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10121884U JPS6117891U (en) | 1984-07-03 | 1984-07-03 | Inverter control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10121884U JPS6117891U (en) | 1984-07-03 | 1984-07-03 | Inverter control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6117891U true JPS6117891U (en) | 1986-02-01 |
Family
ID=30660659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10121884U Pending JPS6117891U (en) | 1984-07-03 | 1984-07-03 | Inverter control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6117891U (en) |
-
1984
- 1984-07-03 JP JP10121884U patent/JPS6117891U/en active Pending
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