JPS60174947U - input/output control device - Google Patents
input/output control deviceInfo
- Publication number
- JPS60174947U JPS60174947U JP6349284U JP6349284U JPS60174947U JP S60174947 U JPS60174947 U JP S60174947U JP 6349284 U JP6349284 U JP 6349284U JP 6349284 U JP6349284 U JP 6349284U JP S60174947 U JPS60174947 U JP S60174947U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- lines
- control device
- required number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input From Keyboards Or The Like (AREA)
- Digital Computer Display Output (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例を示す概略回路構成図、第２図
は第１図のものにおける入出力タイミングを示したタイ
ムチャート図である。
１・・・マイクロコンピュータ、２ａ、３ａ、４ａ
−・・・クロックパルス出力ライン、５ ａ、６ ａ
、 ７ ａ！・・表示出力ライン、８ａ、９ａ・・・
入力ライン、１３．１４・・・マトリックス回路。FIG. 1 is a schematic circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing input/output timing in the circuit shown in FIG. 1... Microcomputer, 2a, 3a, 4a
---Clock pulse output line, 5a, 6a
, 7 a!・Display output line, 8a, 9a...
Input line, 13.14...matrix circuit.
Claims (1)
数のクロックパルス出力ラインと、任意のラインに上記
クロックパルスと同期した表示出力を出す所要数の表示
出力ラインとから表示用のマトリックス回路を構成する
と共に、前記クロックパルス出力ラインと所要数の入力
ラインとから入力用のマトリックス回路を構成し、各ラ
インをマイクロコンピュータの入、出力端子に接続して
なる入出力制御装置。A matrix circuit for display is constructed from a required number of clock pulse output lines that sequentially repeatedly output clock pulses of a fixed period, and a required number of display output lines that output display outputs synchronized with the clock pulses on arbitrary lines. , an input/output control device comprising an input matrix circuit configured from the clock pulse output line and a required number of input lines, each line being connected to input and output terminals of a microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6349284U JPS60174947U (en) | 1984-04-27 | 1984-04-27 | input/output control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6349284U JPS60174947U (en) | 1984-04-27 | 1984-04-27 | input/output control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60174947U true JPS60174947U (en) | 1985-11-20 |
Family
ID=30593690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6349284U Pending JPS60174947U (en) | 1984-04-27 | 1984-04-27 | input/output control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60174947U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0273229U (en) * | 1988-11-24 | 1990-06-05 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53142825A (en) * | 1977-05-18 | 1978-12-12 | Fujitsu Ltd | Keyboard display system |
| JPS58112129A (en) * | 1981-12-24 | 1983-07-04 | Tokyo Electric Co Ltd | Key signal input system for 1-chip microcomputer |
-
1984
- 1984-04-27 JP JP6349284U patent/JPS60174947U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53142825A (en) * | 1977-05-18 | 1978-12-12 | Fujitsu Ltd | Keyboard display system |
| JPS58112129A (en) * | 1981-12-24 | 1983-07-04 | Tokyo Electric Co Ltd | Key signal input system for 1-chip microcomputer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0273229U (en) * | 1988-11-24 | 1990-06-05 |
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