JPS62300U - - Google Patents
Info
- Publication number
- JPS62300U JPS62300U JP9176685U JP9176685U JPS62300U JP S62300 U JPS62300 U JP S62300U JP 9176685 U JP9176685 U JP 9176685U JP 9176685 U JP9176685 U JP 9176685U JP S62300 U JPS62300 U JP S62300U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- terminal
- flop
- pulse
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図はその各部の動作波形を示す波形図、第３図は
シフトレジスタと組合せて使用される従来回路を
示す図である。
６……シフトレジスタ、７……Ｄフリツプ・フ
ロツプ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a waveform diagram showing the operating waveforms of each part, and FIG. 3 is a diagram showing a conventional circuit used in combination with a shift register. 6...Shift register, 7...D flip-flop.
Claims (1)
所定のタイミングで複数個づつ間欠的に与えられ
るクロツクパルスによつて数ステツプづつシフト
させて行くための回路であつて、前記入力パルス
がセツト（又はリセツト）端子に印加され、デー
タ端子にその入力パルスのペデスタルに相当する
一定レベルが与えられるＤフリツプ・フロツプと
、このＤフリツプフロツプの出力が入力端子に印
加されるシフトレジスタとを備え、前記Ｄフリツ
プ・フロツプ及びシフトレジスタの各クロツク端
子に前記クロツクパルスを印加してなるパルスシ
フト回路。 (2) 前記シフトレジスタはＤフリツプ・フロツ
プの縦続接続によつて構成されていることを特徴
とする登録請求の範囲第１項記載のパルスシフト
回路。[Claims for Utility Model Registration] (1) A circuit for shifting an input pulse arriving at an arbitrary timing several steps at a time using a plurality of clock pulses intermittently applied at a predetermined timing, A D flip-flop to which the input pulse is applied to the set (or reset) terminal and a constant level corresponding to the pedestal of the input pulse is applied to the data terminal; and a shift register to which the output of the D flip-flop is applied to the input terminal. and applying the clock pulse to each clock terminal of the D flip-flop and shift register. (2) The pulse shift circuit according to claim 1, wherein the shift register is constructed by cascading D flip-flops.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9176685U JPS62300U (en) | 1985-06-18 | 1985-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9176685U JPS62300U (en) | 1985-06-18 | 1985-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62300U true JPS62300U (en) | 1987-01-06 |
Family
ID=30647945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9176685U Pending JPS62300U (en) | 1985-06-18 | 1985-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62300U (en) |
-
1985
- 1985-06-18 JP JP9176685U patent/JPS62300U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62300U (en) | ||
| JPH0357630U (en) | ||
| JPS60174947U (en) | input/output control device | |
| JPS633629U (en) | ||
| JPH0257630U (en) | ||
| JPS60129748U (en) | pulse width modulation circuit | |
| JPH01147441U (en) | ||
| JPS6239300U (en) | ||
| JPS5957033U (en) | Specified number pulse generation circuit | |
| JPH0216617U (en) | ||
| JPS599638U (en) | Simple D/A converter | |
| JPS5936627U (en) | Clock pulse extraction circuit | |
| JPS62105627U (en) | ||
| JPS6392422U (en) | ||
| JPS63108235U (en) | ||
| JPS62103324U (en) | ||
| JPS60103940U (en) | Frequency divider circuit | |
| JPS58109339U (en) | Gate pulse generation circuit | |
| JPS6117891U (en) | Inverter control device | |
| JPH01159424U (en) | ||
| JPS5952763U (en) | Control clock pulse and dial pulse generator | |
| JPH0357629U (en) | ||
| JPS6335324U (en) | ||
| JPS6079834U (en) | Clock pulse detection circuit | |
| JPS6381532U (en) |