JPS6079834U - Clock pulse detection circuit - Google Patents
Clock pulse detection circuitInfo
- Publication number
- JPS6079834U JPS6079834U JP17295083U JP17295083U JPS6079834U JP S6079834 U JPS6079834 U JP S6079834U JP 17295083 U JP17295083 U JP 17295083U JP 17295083 U JP17295083 U JP 17295083U JP S6079834 U JPS6079834 U JP S6079834U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- clock pulse
- output
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例回路を示すブロック構成図。第２図は第
１図に示す回路の各部の信号波形図。第３図は実施例回
路を示すブロック構成図。第４図は第３図に示す回路の
各部の信号波形図。
１１・・・遅延回路、１２・・・反転出力排他的論理和
回路、１３．１４・・・フリップフロップ、３１・・・
シフトレジスタ、３２，３３．３８・・・ナンド回路、
３４．３５，３６，５７・・・フリップフロップ。FIG. 1 is a block diagram showing a conventional circuit. FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1. FIG. 3 is a block configuration diagram showing an example circuit. FIG. 4 is a signal waveform diagram of each part of the circuit shown in FIG. 3. 11...Delay circuit, 12...Inverted output exclusive OR circuit, 13.14...Flip-flop, 31...
Shift register, 32, 33. 38... NAND circuit,
34.35,36,57...Flip-flop.
Claims (1)
トレジスタと、 前記シフトレジスタの並列出力の論理積をとる論理積回
路と、 前記論理積出力によりセットされる第一のフリップフロ
ップと、 前記第一のフリップフロップの出力を所望の読み出し周
期でサンプリングする第二９フリツプフロツプと を備え、 前記第一のフリップフロップは前記読み出し周期でリセ
ットされるように構成され、前記第二のフリップフロッ
プ出力をクロックパルスの断続検出出力とするクロック
パルス検出回路。[Claims for Utility Model Registration] A serial input/parallel output type shift register that receives clock pulses as input; an AND circuit that takes an AND of parallel outputs of the shift register; and a first circuit that is set by the AND output. a second flip-flop that samples the output of the first flip-flop at a desired readout period, the first flip-flop is configured to be reset at the readout period, and the first flip-flop is configured to be reset at the readout period; A clock pulse detection circuit that uses the second flip-flop output as a clock pulse intermittent detection output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17295083U JPS6079834U (en) | 1983-11-08 | 1983-11-08 | Clock pulse detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17295083U JPS6079834U (en) | 1983-11-08 | 1983-11-08 | Clock pulse detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6079834U true JPS6079834U (en) | 1985-06-03 |
Family
ID=30376877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17295083U Pending JPS6079834U (en) | 1983-11-08 | 1983-11-08 | Clock pulse detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6079834U (en) |
-
1983
- 1983-11-08 JP JP17295083U patent/JPS6079834U/en active Pending
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