JPS61160556U - - Google Patents
Info
- Publication number
- JPS61160556U JPS61160556U JP4258485U JP4258485U JPS61160556U JP S61160556 U JPS61160556 U JP S61160556U JP 4258485 U JP4258485 U JP 4258485U JP 4258485 U JP4258485 U JP 4258485U JP S61160556 U JPS61160556 U JP S61160556U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- counter
- clock pulse
- inputs
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control By Computers (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
。第２図はこの考案のアドレス設定装置における
各部信号を示すタイムチヤート、第３図は従来の
アドレス設定装置を示すブロツク図、第４図は従
来のアドレス設定装置における各部信号を示すタ
イムチヤートである。
図において１は第１のアドレス設定装置、２は
第２のアドレス設定装置、３はクロツクパルス、
４，５はシフトレジスタ回路、６，７はレジスタ
回路、８は直列アドレス信号、９はシフトレジス
タ直列出力信号、１０，１１はシフトレジスタ並
列出力信号、１２はセツト信号、１３，１４はア
ドレス、１５，１６はカウンタ回路、１７，１８
，１９，２０はフリツプフロツプ回路、２１，２
２はインバータ、２３はリセツト信号、２４は外
部からのイネーブル信号、２５，２９はフリツプ
フロツプ出力、２７は第１のイネーブル信号、２
８，３１はカウンタ出力、３０は第２のイネーブ
ル信号である。なお各図中同一符号は同一または
相当部分を示す。
FIG. 1 is a block diagram showing one embodiment of this invention. Fig. 2 is a time chart showing the signals of each part in the address setting device of this invention, Fig. 3 is a block diagram showing the conventional address setting device, and Fig. 4 is a time chart showing the signals of each part in the conventional address setting device. . In the figure, 1 is a first address setting device, 2 is a second address setting device, 3 is a clock pulse,
4 and 5 are shift register circuits, 6 and 7 are register circuits, 8 is a serial address signal, 9 is a shift register serial output signal, 10 and 11 are shift register parallel output signals, 12 is a set signal, 13 and 14 are addresses, 15, 16 are counter circuits, 17, 18
, 19, 20 are flip-flop circuits, 21, 2
2 is an inverter, 23 is a reset signal, 24 is an external enable signal, 25 and 29 are flip-flop outputs, 27 is a first enable signal, 2
8 and 31 are counter outputs, and 30 is a second enable signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
回数を数え、この回数を２進数で表わして出力す
るカウンタ回路と、このカウンタの出力を入力し
設定するレジスタ回路と、外部から入力される信
号を上記クロツクパルスに同期させて出力するフ
リツプフロツプ回路とを備え、上記カウンタ回路
の出力をアドレスとして使用することを特徴とし
たアドレス設定装置。 A counter circuit that counts the number of times a clock pulse is manipulated at a constant cycle and outputs this number as a binary number; a register circuit that inputs and sets the output of this counter; and a register circuit that inputs an externally input signal to the clock pulse. An address setting device comprising a flip-flop circuit that outputs data in synchronization, and using the output of the counter circuit as an address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4258485U JPS61160556U (en) | 1985-03-25 | 1985-03-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4258485U JPS61160556U (en) | 1985-03-25 | 1985-03-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61160556U true JPS61160556U (en) | 1986-10-04 |
Family
ID=30553476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4258485U Pending JPS61160556U (en) | 1985-03-25 | 1985-03-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61160556U (en) |
-
1985
- 1985-03-25 JP JP4258485U patent/JPS61160556U/ja active Pending
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