JPH0260331U - - Google Patents
Info
- Publication number
- JPH0260331U JPH0260331U JP13837088U JP13837088U JPH0260331U JP H0260331 U JPH0260331 U JP H0260331U JP 13837088 U JP13837088 U JP 13837088U JP 13837088 U JP13837088 U JP 13837088U JP H0260331 U JPH0260331 U JP H0260331U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- throttling
- input
- alternating
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は単位しぼり込み回路の組合せ実施例回
路構成図、第２図は単位しぼり込み回路の実施例
回路図、第３図は同上タイムチヤート。
１：Ｄフリツプフロツプ回路、２：デイレイ回
路、３：単位しぼり込み回路、ＣＫ：クロツク端
子、ＲＳＴ：リセツト端子。
FIG. 1 is a circuit configuration diagram of a combination example of a unit restriction circuit, FIG. 2 is a circuit diagram of an example of a unit restriction circuit, and FIG. 3 is a time chart of the same. 1: D flip-flop circuit, 2: delay circuit, 3: unit throttling circuit, CK: clock terminal, RST: reset terminal.
Claims (1)
交番信号をデイレイ回路を介してＦ／Ｆ（フリツ
プフロツプ）回路のＣＫ（クロツク）端子に入力
し、他方の交番信号を前記Ｆ／Ｆ回路のＲＳＴ（
リセツト）端子もしくはＳＥＴ（セツト）端子に
入力する構成よりなる回路を１つのしぼり込み回
路とし、該しぼり込み回路を単位のしぼり込み回
路として、複数の同期して動作する交番信号のう
ち２つの交番信号を前記しぼり込み回路に入力し
、該しぼり込み回路の出力を次段のしぼり込み回
路に入力し、順次重ね合せ、１つの交番信号とし
てしぼり込み出力することができることを特徴と
する交番信号のしぼり込み回路。 One of the two alternating signals that operate synchronously is input to the CK (clock) terminal of the F/F (flip-flop) circuit via a delay circuit, and the other alternating signal is input to the RST of the F/F circuit. (
A circuit configured to input to the (reset) terminal or the SET (set) terminal is regarded as one narrowing circuit, and the narrowing circuit is used as a unit narrowing circuit to output two alternating signals from among a plurality of alternating signals that operate synchronously. A signal is input to the throttling circuit, the output of the throttling circuit is inputted to the throttling circuit at the next stage, and the signals are sequentially superimposed and the throttling is outputted as one alternating signal. Squeezing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13837088U JPH0260331U (en) | 1988-10-24 | 1988-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13837088U JPH0260331U (en) | 1988-10-24 | 1988-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0260331U true JPH0260331U (en) | 1990-05-02 |
Family
ID=31400644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13837088U Pending JPH0260331U (en) | 1988-10-24 | 1988-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0260331U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54122080A (en) * | 1978-03-15 | 1979-09-21 | Nec Corp | Chattering eliminator circuit |
-
1988
- 1988-10-24 JP JP13837088U patent/JPH0260331U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54122080A (en) * | 1978-03-15 | 1979-09-21 | Nec Corp | Chattering eliminator circuit |
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