JPS62147929U - - Google Patents
Info
- Publication number
- JPS62147929U JPS62147929U JP3635186U JP3635186U JPS62147929U JP S62147929 U JPS62147929 U JP S62147929U JP 3635186 U JP3635186 U JP 3635186U JP 3635186 U JP3635186 U JP 3635186U JP S62147929 U JPS62147929 U JP S62147929U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- signal
- capacitor
- supplied
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の一例の構成図、第２図は他の
例の構成図、第３図は従来の技術の説明のための
図である。
１，４は端子、３，５，８はスイツチ、６はコ
ンデンサ、７はインバータアンプ、１４はクロツ
ク信号端子、１５〜１８は遅延回路である。
FIG. 1 is a block diagram of one example of the present invention, FIG. 2 is a block diagram of another example, and FIG. 3 is a diagram for explaining a conventional technique. 1 and 4 are terminals, 3, 5, and 8 are switches, 6 is a capacitor, 7 is an inverter amplifier, 14 is a clock signal terminal, and 15 to 18 are delay circuits.
Claims (1)
、参照電位端子が第２のスイツチを通じて互いに
接続されてコンデンサの一端に接続され、 このコンデンサの他端がインバータアンプの入
力に接続されると共にこのインバータアンプの入
出力間が第３のスイツチを通じて接続されてなり
、 上記第３のスイツチの駆動信号で遅延されて上
記第２のスイツチに同相で供給されると共に、上
記第１のスイツチに逆相で供給されるようにした
チヨツパ型コンパレータ。[Claims for Utility Model Registration] The signal potential terminal passes through the first switch, and the reference potential terminals are connected to each other through a second switch and connected to one end of a capacitor, and the other end of this capacitor is connected to the input of the inverter amplifier. and the input and output of this inverter amplifier are connected through a third switch, and the signal is delayed by the drive signal of the third switch and is supplied to the second switch in the same phase. A chipper type comparator that is supplied with reverse phase to switch 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3635186U JPS62147929U (en) | 1986-03-13 | 1986-03-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3635186U JPS62147929U (en) | 1986-03-13 | 1986-03-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62147929U true JPS62147929U (en) | 1987-09-18 |
Family
ID=30846673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3635186U Pending JPS62147929U (en) | 1986-03-13 | 1986-03-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62147929U (en) |
-
1986
- 1986-03-13 JP JP3635186U patent/JPS62147929U/ja active Pending
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