JPS62151223U - - Google Patents

Info

Publication number
JPS62151223U
JPS62151223U JP3745386U JP3745386U JPS62151223U JP S62151223 U JPS62151223 U JP S62151223U JP 3745386 U JP3745386 U JP 3745386U JP 3745386 U JP3745386 U JP 3745386U JP S62151223 U JPS62151223 U JP S62151223U
Authority
JP
Japan
Prior art keywords
switch
mos
gate
turned
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3745386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3745386U priority Critical patent/JPS62151223U/ja
Publication of JPS62151223U publication Critical patent/JPS62151223U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一例の構成図、第2図〜第5
図はその説明のための図、第6図は従来の技術の
説明のための図である。 1は入力端子、2,7,8はスイツチ、3,5
はMOS素子、4は電源端子、6は出力端子、9
はコンデンサである。
Figure 1 is a configuration diagram of an example of the present invention, Figures 2 to 5
The figure is a diagram for explaining the same, and FIG. 6 is a diagram for explaining the conventional technique. 1 is an input terminal, 2, 7, 8 are switches, 3, 5
is a MOS element, 4 is a power supply terminal, 6 is an output terminal, 9
is a capacitor.

Claims (1)

【実用新案登録請求の範囲】 第1及び第2のMOS素子が電源と接地間に直
列に接続され、 入力端子が第1のスイツチを介して上記第1の
MOS素子のゲートに接続されると共に上記第1
のMOS素子のゲートソース間に第2のスイツチ
が接続され、 上記第1、第2のMOS素子の接続中点から出
力端子が導出され、 この出力端子が第3のスイツチを介して上記第
2のMOS素子のゲートに接続されると共に上記
第2のMOS素子のゲートソース間にコンデンサ
が接続されてなり、 上記入力端子に供給される信号の有効期間に上
記第1のスイツチがオンされ、上記供給される信
号の非有効期間に上記第2、第3のスイツチがオ
ンされるようにしたことを特徴とするバツフア回
路。
[Claims for Utility Model Registration] First and second MOS devices are connected in series between a power source and ground, and an input terminal is connected to the gate of the first MOS device via a first switch. 1st above
A second switch is connected between the gate and source of the MOS element, and an output terminal is derived from the connection midpoint of the first and second MOS elements, and this output terminal is connected to the second MOS element via a third switch. and a capacitor is connected between the gate and the source of the second MOS element, and the first switch is turned on during the valid period of the signal supplied to the input terminal, and the first switch is turned on during the valid period of the signal supplied to the input terminal. A buffer circuit characterized in that the second and third switches are turned on during an ineffective period of the supplied signal.
JP3745386U 1986-03-14 1986-03-14 Pending JPS62151223U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3745386U JPS62151223U (en) 1986-03-14 1986-03-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3745386U JPS62151223U (en) 1986-03-14 1986-03-14

Publications (1)

Publication Number Publication Date
JPS62151223U true JPS62151223U (en) 1987-09-25

Family

ID=30848792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3745386U Pending JPS62151223U (en) 1986-03-14 1986-03-14

Country Status (1)

Country Link
JP (1) JPS62151223U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008206195A (en) * 2002-01-17 2008-09-04 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2011250462A (en) * 2001-11-28 2011-12-08 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic equipment

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011250462A (en) * 2001-11-28 2011-12-08 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic equipment
JP2013102465A (en) * 2001-11-28 2013-05-23 Semiconductor Energy Lab Co Ltd Semiconductor device
US8536937B2 (en) 2001-11-28 2013-09-17 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
JP2013232898A (en) * 2001-11-28 2013-11-14 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2014096806A (en) * 2001-11-28 2014-05-22 Semiconductor Energy Lab Co Ltd Semiconductor device
US8841941B2 (en) 2001-11-28 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
JP2014239530A (en) * 2001-11-28 2014-12-18 株式会社半導体エネルギー研究所 Semiconductor device
JP2008206195A (en) * 2002-01-17 2008-09-04 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2011205699A (en) * 2002-01-17 2011-10-13 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus
JP2013176143A (en) * 2002-01-17 2013-09-05 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus

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