JPS6057225U - Digital signal input circuit - Google Patents
Digital signal input circuitInfo
- Publication number
- JPS6057225U JPS6057225U JP14915783U JP14915783U JPS6057225U JP S6057225 U JPS6057225 U JP S6057225U JP 14915783 U JP14915783 U JP 14915783U JP 14915783 U JP14915783 U JP 14915783U JP S6057225 U JPS6057225 U JP S6057225U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- input circuit
- digital signal
- signal input
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデジタル信号入力回路の一例の回路図、
第２図は同人力回路のタイミングチャートを示す。また
第３図はこの考案の実施例であるデジタル信号入力回路
の回路図、第４図は同人力回路のタイミングチャートを
示す。
ＦＦＩ〜ＦＦ４−フリップフロップ、６１〜Ｇ４−ヶ゛
−ト。
Ｇ１０ＵＴノ
正常出力
′フFigure 1 is a circuit diagram of an example of a conventional digital signal input circuit.
FIG. 2 shows a timing chart of the human-powered circuit. Further, FIG. 3 shows a circuit diagram of a digital signal input circuit which is an embodiment of this invention, and FIG. 4 shows a timing chart of the same human-powered circuit. FFI~FF4-flip flop, 61~G4-gate. G10UT normal output
Claims (1)
リップフロップをクロックで順次反転していき、各フリ
ップフロップの出力を論理積することにより出力信号を
得るデジタル信号入力回路において、Ｎ番目のフリップ
フロップ出力と、Ｎ十ｎ番目のフリップフロップ出力と
、入力信号とを論理積し、その論理積をする期間内に入
力信号が反転したときＮ番目以前のフリップフロップの
何れかを初期状態に戻すことを特徴とするデジタル信号
入力回路。In a digital signal input circuit that sequentially inverts multiple cascaded flip-flops using a clock when receiving a digital input signal, and obtains an output signal by ANDing the outputs of each flip-flop, the Nth flip-flop To AND the output, the N10nth flip-flop output, and the input signal, and return any of the Nth and earlier flip-flops to the initial state when the input signal is inverted within the period of ANDing. A digital signal input circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14915783U JPS6057225U (en) | 1983-09-27 | 1983-09-27 | Digital signal input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14915783U JPS6057225U (en) | 1983-09-27 | 1983-09-27 | Digital signal input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6057225U true JPS6057225U (en) | 1985-04-22 |
| JPH0238511Y2 JPH0238511Y2 (en) | 1990-10-17 |
Family
ID=30331184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14915783U Granted JPS6057225U (en) | 1983-09-27 | 1983-09-27 | Digital signal input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6057225U (en) |
-
1983
- 1983-09-27 JP JP14915783U patent/JPS6057225U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0238511Y2 (en) | 1990-10-17 |
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