JPS5890593U - electronic display circuit device - Google Patents
electronic display circuit deviceInfo
- Publication number
- JPS5890593U JPS5890593U JP16870981U JP16870981U JPS5890593U JP S5890593 U JPS5890593 U JP S5890593U JP 16870981 U JP16870981 U JP 16870981U JP 16870981 U JP16870981 U JP 16870981U JP S5890593 U JPS5890593 U JP S5890593U
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- circuit
- clear
- electronic display
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の電子表示回路装置の一実施例１ を示
す回路図、第２図は第１図に示す電子表示回路装置にお
ける各点のタイミングチャート図、第３図は第１図に示
す発光表示素子を示す概略図である。
１．２・・・・・・シフトレジスタ、３・・・・・一端
子、４−・・・・・クロック発振回路、５． ６． ７
． ８． ９． １１・・・・・・インバータ、１０・
・・・・・スイッチ、Ｒ１−Ｒ１４・・・・・・抵抗、
Ｃ・・・・・・コンデンサ、Ｄ１〜Ｄ８・・・・・・発
光表示素子、Ｄ９〜Ｄ１゜・・・・・・ダイオード。FIG. 1 is a circuit diagram showing Embodiment 1 of the electronic display circuit device of the present invention, FIG. 2 is a timing chart of each point in the electronic display circuit device shown in FIG. 1, and FIG. 3 is similar to FIG. 1 is a schematic diagram showing a light emitting display element shown in FIG. 1.2...Shift register, 3...One terminal, 4-...Clock oscillation circuit, 5. 6. 7
．． 8. 9. 11... Inverter, 10.
...Switch, R1-R14...Resistance,
C... Capacitor, D1-D8... Light-emitting display element, D9-D1°... Diode.
Claims (1)
成され入力信号を複数の出力端Ｑ、、 Ｑ２・・・・・
−Ｑｎに前記クロック発振回路のクロックパルスによっ
て順次出力する２個のシフトレジスタと、これらのシフ
トレジスタの各出力端に接続された表示素子と、互いに
一方のシフトレジスタのＱｎｎ日日出力端と他方のシフ
トレジスタのクリア端子間に各々接続されたインバータ
と、互いに一方のシフトレジスタのＱ、番目の出力端と
他方のシフトレジスタのクリア端子間を相互に接続して
前記Ｑ□番目の出力を他方のシフトレジスタのクリアパ
ルスとして相互に加える回路と、各シフトレジスタのク
リア端子に接続され各シフトレジスタを切換動作させる
スイッチ回路とを具備することを特徴とする電子表示回
路装置。Consisting of a clock oscillation circuit and a D-flip-flop circuit, input signals are sent to multiple output terminals Q, Q2...
- two shift registers that sequentially output signals to Qn in response to clock pulses from the clock oscillation circuit; a display element connected to each output terminal of these shift registers; and inverters connected between the clear terminals of the shift registers, respectively, and the Q,th output terminal of one shift register and the clear terminal of the other shift register are mutually connected, and the Q□th output is connected to the other shift register. What is claimed is: 1. An electronic display circuit device comprising: a circuit for mutually applying clear pulses to the shift registers; and a switch circuit connected to a clear terminal of each shift register to switch each shift register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16870981U JPS5890593U (en) | 1981-11-12 | 1981-11-12 | electronic display circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16870981U JPS5890593U (en) | 1981-11-12 | 1981-11-12 | electronic display circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5890593U true JPS5890593U (en) | 1983-06-18 |
Family
ID=29960737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16870981U Pending JPS5890593U (en) | 1981-11-12 | 1981-11-12 | electronic display circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5890593U (en) |
-
1981
- 1981-11-12 JP JP16870981U patent/JPS5890593U/en active Pending
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