JPS59122629U - Digital circuit push button input device - Google Patents
Digital circuit push button input deviceInfo
- Publication number
- JPS59122629U JPS59122629U JP1802383U JP1802383U JPS59122629U JP S59122629 U JPS59122629 U JP S59122629U JP 1802383 U JP1802383 U JP 1802383U JP 1802383 U JP1802383 U JP 1802383U JP S59122629 U JPS59122629 U JP S59122629U
- Authority
- JP
- Japan
- Prior art keywords
- push button
- digital circuit
- input device
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input From Keyboards Or The Like (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の回路図、第２図は本考案の一実施例を
示す回路図、第３図は同上の各部波形図である。
ＶＤＤは直流電源、Ｒはプルアップ抵抗、Ｓはスイッチ
ング素子、Ｂは押釦スイッチ、ＸＯＲは排他的論理和回
路、ＦＦはフリップフロップ、ＯＳＣはパルス発振器。FIG. 1 is a circuit diagram of a conventional example, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram of each part of the same. VDD is a DC power supply, R is a pull-up resistor, S is a switching element, B is a push button switch, XOR is an exclusive OR circuit, FF is a flip-flop, and OSC is a pulse oscillator.
Claims (1)
グ素子および押釦スイッチを直列に接続し、スイッチン
グ素子の制御端子にクロックパルスを印加して、スイッ
チング素子の出力とクロックパルスとを入力する排他的
論理和回路を設け、上鮎スイッチング素子の出力でセッ
トされ、上記排他的論理和回路の出力でリセットされる
フリップフロップの出力をデジタル回路の入力信号とし
て成るデジタル回路の押釦入力装置。Exclusive logic that connects a pull-up resistor, a switching element, and a push button switch in series between a DC power source and ground, applies a clock pulse to the control terminal of the switching element, and inputs the output of the switching element and the clock pulse. A push button input device for a digital circuit, which is provided with a sum circuit, and uses the output of a flip-flop, which is set by the output of the above-mentioned exclusive OR circuit and reset by the output of the exclusive OR circuit, as an input signal to the digital circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1802383U JPS59122629U (en) | 1983-02-08 | 1983-02-08 | Digital circuit push button input device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1802383U JPS59122629U (en) | 1983-02-08 | 1983-02-08 | Digital circuit push button input device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59122629U true JPS59122629U (en) | 1984-08-18 |
Family
ID=30149242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1802383U Pending JPS59122629U (en) | 1983-02-08 | 1983-02-08 | Digital circuit push button input device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59122629U (en) |
-
1983
- 1983-02-08 JP JP1802383U patent/JPS59122629U/en active Pending
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