JPS59164338U - Noise prevention circuit - Google Patents
Noise prevention circuitInfo
- Publication number
- JPS59164338U JPS59164338U JP5663083U JP5663083U JPS59164338U JP S59164338 U JPS59164338 U JP S59164338U JP 5663083 U JP5663083 U JP 5663083U JP 5663083 U JP5663083 U JP 5663083U JP S59164338 U JPS59164338 U JP S59164338U
- Authority
- JP
- Japan
- Prior art keywords
- prevention circuit
- noise prevention
- diode
- reference voltage
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す回路図、第２区は上記
実施例の正常時および入力断時における各都電圧を示す
タイムチャートである。
図において、１．２・・・受信端子、３・・・出力端子
、４．５・・・終端抵抗、６・・・ＥＣＬ差動信号受信
回路、７・・・ダイオード、９・・・基準電圧端子、１
０．１１・・・差動入力端子、２１．２２・・・差動入
力端子の電位、２３・・・出力端子の電位、Ｖｅ・・・
終端用電源、Ｖｒｅｆ・・・基準電圧、ｖＲｏＰ・・・
ダイオードの順方向電圧。FIG. 1 is a circuit diagram showing one embodiment of the present invention, and the second section is a time chart showing voltages at various points in the above embodiment during normal operation and when input is cut off. In the figure, 1.2...Reception terminal, 3...Output terminal, 4.5...Terminal resistor, 6...ECL differential signal receiving circuit, 7...Diode, 9...Reference Voltage terminal, 1
0.11... Differential input terminal, 21.22... Potential of differential input terminal, 23... Potential of output terminal, Ve...
Termination power supply, Vref...reference voltage, vRoP...
Diode forward voltage.
Claims (1)
差動入力端子のいずれか１方がダイオードを介して基準
電圧端子に接続され、上記ダイオードは無人力時に順方
向となる極性であることを特徴とする雑音防止回路。In emitter-coupled logic integrated circuits for differential signal reception,
1. A noise prevention circuit, wherein one of the differential input terminals is connected to a reference voltage terminal via a diode, and the diode has a forward polarity when no power is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5663083U JPS59164338U (en) | 1983-04-18 | 1983-04-18 | Noise prevention circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5663083U JPS59164338U (en) | 1983-04-18 | 1983-04-18 | Noise prevention circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59164338U true JPS59164338U (en) | 1984-11-05 |
Family
ID=30186952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5663083U Pending JPS59164338U (en) | 1983-04-18 | 1983-04-18 | Noise prevention circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59164338U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53255A (en) * | 1976-06-24 | 1978-01-05 | Akira Ikeda | Method of simultaneously molding with multiple colors |
-
1983
- 1983-04-18 JP JP5663083U patent/JPS59164338U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53255A (en) * | 1976-06-24 | 1978-01-05 | Akira Ikeda | Method of simultaneously molding with multiple colors |
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