JPS6064633U - switch input circuit - Google Patents
switch input circuitInfo
- Publication number
- JPS6064633U JPS6064633U JP1983157817U JP15781783U JPS6064633U JP S6064633 U JPS6064633 U JP S6064633U JP 1983157817 U JP1983157817 U JP 1983157817U JP 15781783 U JP15781783 U JP 15781783U JP S6064633 U JPS6064633 U JP S6064633U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- power source
- resistor
- diode
- pull
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
- Keying Circuit Devices (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図り従来の時計回路等ｉこおけるスイッチ入力回路
図、第２図は本考案の一実施例を示す時計回路のスイッ
チ入カー略図、第３図は他の実施例を示す第２図同様ス
イッチ入力回路図である。Fig. 1 is a switch input circuit diagram of a conventional clock circuit, etc. Fig. 2 is a schematic diagram of a switch input circuit of a clock circuit showing one embodiment of the present invention, Fig. 3 is similar to Fig. 2 showing another embodiment. FIG. 3 is a switch input circuit diagram.
Claims (1)
れた第１の信号入力端子２１に、一端がダイオード１６
のアノードに接続された第１のスイッチ１４の他端全接
続し、かつ第２のプルアップ抵抗９を介して前記電源１
の正極に接続された第２の信号入力端子２２に、ベース
が前記第１のプルアップ抵抗８の抵抗値より大きな抵抗
値のベース抵抗１８を介して前記第１のスイッチ１４と
前記ダイオード１６との接続点に接続され、エミッタが
前記電源１の負極に接続されたトランジスタ１７のコレ
クタを接続し、かつ第３のプルアップ抵抗１９を介して
前記電源１の正極に接続された第３の信号入力端子２３
に、前記ダイオード１− ６のカソードを接続する
と共に、一端が前記電源、１の負極に接続された第２の
スイッチ１５の他端を接続したことを特門とするスイッ
チ入力回路。A diode 16 is connected to the first signal input terminal 21 connected to the positive electrode of the power supply 1 via the first pull-up resistor 8.
The other end of the first switch 14 connected to the anode of the power source 1 is fully connected, and the power source 1 is
The first switch 14 and the diode 16 are connected to the second signal input terminal 22 connected to the positive terminal of the first switch 14 and the diode 16 via a base resistor 18 whose base has a resistance value greater than the resistance value of the first pull-up resistor 8. a third signal connected to the connection point of the transistor 17 whose emitter is connected to the negative electrode of the power source 1, and connected to the positive electrode of the power source 1 via a third pull-up resistor 19; Input terminal 23
The switch input circuit is characterized in that the cathodes of the diodes 1-6 are connected to the diodes 1-6, and the other end of the second switch 15, one end of which is connected to the negative electrode of the power source 1, is connected to the other end of the second switch 15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983157817U JPS6064633U (en) | 1983-10-11 | 1983-10-11 | switch input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983157817U JPS6064633U (en) | 1983-10-11 | 1983-10-11 | switch input circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6064633U true JPS6064633U (en) | 1985-05-08 |
Family
ID=30347837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983157817U Pending JPS6064633U (en) | 1983-10-11 | 1983-10-11 | switch input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6064633U (en) |
-
1983
- 1983-10-11 JP JP1983157817U patent/JPS6064633U/en active Pending
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