JPS5816921U - level conversion circuit - Google Patents
level conversion circuitInfo
- Publication number
- JPS5816921U JPS5816921U JP10773381U JP10773381U JPS5816921U JP S5816921 U JPS5816921 U JP S5816921U JP 10773381 U JP10773381 U JP 10773381U JP 10773381 U JP10773381 U JP 10773381U JP S5816921 U JPS5816921 U JP S5816921U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- transistor
- power supply
- conversion circuit
- level conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のレベル変換回路、第２図は本考案の実施
例によるレベル変換回路、第３図は本考案の入力、出力
波形図、第４図はツェナーダイオードの電圧−電流特性
を示す。
１、 ３． ４． ８． １０． １２． １４：抵抗
、５：コンデンサ、２．１３＝トランジスタ、６：ダイ
オード、９．１１：ツェナーダイオード、７：コンパレ
ータ、１５：インバータ。Fig. 1 shows a conventional level conversion circuit, Fig. 2 shows a level conversion circuit according to an embodiment of the present invention, Fig. 3 shows an input and output waveform diagram of the present invention, and Fig. 4 shows voltage-current characteristics of a Zener diode. . 1, 3. 4. 8. 10. 12. 14: Resistor, 5: Capacitor, 2.13 = Transistor, 6: Diode, 9.11: Zener diode, 7: Comparator, 15: Inverter.
Claims (1)
ると共に、入力信号が印加されるようになっており該第
１のトランジスタのコレク多は正電源に接続し、第１の
トランジメタのエミッタは抵抗３を介して負電源に接続
すると共に抵抗１０を介してツェナーダイオードのアノ
ードに接続し、ツェナーダイオードのカソードは抵抗１
２を介して正電源に接続すると共に第２゛めトランジス
タの−ベースに接続し第２のトランジスタのエミッタは
正電源に接続し第２のトランジスタのコレクタは抵抗１
４を介して接地すると共に信号が出力するように構成し
ている回路で、前記ツェナーダイオードをスイッチング
させるように構成していることを特徴とするレベル変換
回路。The base of the first transistor is grounded via a resistor 1, and an input signal is applied to it.The collector of the first transistor is connected to the positive power supply, and the emitter of the first transistor is connected to the positive power supply. is connected to the negative power supply through resistor 3 and to the anode of the Zener diode through resistor 10, and the cathode of the Zener diode is connected to resistor 1.
The emitter of the second transistor is connected to the positive power supply, and the collector of the second transistor is connected to the positive power supply through the resistor 1.
4. A level conversion circuit, characterized in that the circuit is configured so as to be grounded through a terminal 4 and to output a signal, and is configured to switch the Zener diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10773381U JPS5816921U (en) | 1981-07-22 | 1981-07-22 | level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10773381U JPS5816921U (en) | 1981-07-22 | 1981-07-22 | level conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5816921U true JPS5816921U (en) | 1983-02-02 |
Family
ID=29902161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10773381U Pending JPS5816921U (en) | 1981-07-22 | 1981-07-22 | level conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5816921U (en) |
-
1981
- 1981-07-22 JP JP10773381U patent/JPS5816921U/en active Pending
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