JPS60149250U - Malfunction prevention circuit - Google Patents
Malfunction prevention circuitInfo
- Publication number
- JPS60149250U JPS60149250U JP3410784U JP3410784U JPS60149250U JP S60149250 U JPS60149250 U JP S60149250U JP 3410784 U JP3410784 U JP 3410784U JP 3410784 U JP3410784 U JP 3410784U JP S60149250 U JPS60149250 U JP S60149250U
- Authority
- JP
- Japan
- Prior art keywords
- bias resistor
- malfunction prevention
- subsequent circuit
- prevention circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案め一実施例の回路図である。 、１・・
・電圧Ａを有する電源、２・・・電圧Ｂを有する電源、
３・・・論理回路、４・・・論理回路、５・・・論理出
力端子、“６・・・論理入力端子、７〜９・・・バイア
ス抵抗ミ １０・・・ツェナダイオード、１１・・・Ｐ
ＮＰ ）ランジスタ、１２・・・ＮＰＮ トランジスタ
。The figure is a circuit diagram of one embodiment of the present invention. ,1...
-Power supply having voltage A, 2...Power supply having voltage B,
3...Logic circuit, 4...Logic circuit, 5...Logic output terminal, "6...Logic input terminal, 7-9...Bias resistance mi 10...Zena diode, 11...・P
NP) transistor, 12...NPN transistor.
Claims (1)
要のある論理回路において、コレクタが後続回路の電源
に接続されているＰＮＰ トランジス□ タおよび
エミッタがアースに接続されているＮＰＮ ）ランジス
タのベース同志を、前者はバイアス抵抗およびツェナダ
イオードを介し、後者はバイアス抵抗のみを介し接続し
、これを更に別なバイアス抵抗を介して入力とし、一方
コレクタ同志を接続して出力とし、後続回路の駆動イン
ピーダンスを小さくした上で論理値の電圧シフトを実現
する事を特徴とする誤動作防止回路。In logic circuits where the voltage of a logic signal needs to be shifted and transmitted to the subsequent circuit, the base of the PNP transistor whose collector is connected to the power supply of the subsequent circuit (NPN whose collector and emitter are connected to ground) The former is connected through a bias resistor and a Zener diode, and the latter is connected through only a bias resistor, and this is used as an input through another bias resistor, while the collectors are connected together and used as an output to drive the subsequent circuit. A malfunction prevention circuit that is characterized by realizing voltage shift of logical values while reducing impedance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3410784U JPS60149250U (en) | 1984-03-12 | 1984-03-12 | Malfunction prevention circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3410784U JPS60149250U (en) | 1984-03-12 | 1984-03-12 | Malfunction prevention circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60149250U true JPS60149250U (en) | 1985-10-03 |
Family
ID=30537169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3410784U Pending JPS60149250U (en) | 1984-03-12 | 1984-03-12 | Malfunction prevention circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60149250U (en) |
-
1984
- 1984-03-12 JP JP3410784U patent/JPS60149250U/en active Pending
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