JPS6090938U - logic circuit - Google Patents
logic circuitInfo
- Publication number
- JPS6090938U JPS6090938U JP18348183U JP18348183U JPS6090938U JP S6090938 U JPS6090938 U JP S6090938U JP 18348183 U JP18348183 U JP 18348183U JP 18348183 U JP18348183 U JP 18348183U JP S6090938 U JPS6090938 U JP S6090938U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- logic circuit
- collector
- base
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の論理回路の代表的な一例を示す回路図お
よび第２図は本考案の論理回路の一実施例を示す回路図
である。
図において、１・・・・・・前段論理回路部、２・・・
・・・出力回路部、３． ５．７． ９． ９’、
９“、１０・・・・・・抵抗、４・・・・・・内部出力
段トランジスタ、６・・・・・・インバータトランジス
タ、８・・・・・・オフバッファ前段トランジスタ、１
１・・・・・・オフバッファ後段トランジスタ、１２・
・・・・・出力トランジスタ、１３・・・・・・ベース
・コレクタ間接合容量、１４・・・・・・電源端子（ｖ
ｏｃ）、１５・・・・・・出力端子、１６・・・・・・
接地端子（ＧＮＤ）、１７・・・・・・プルダウントラ
ンジスタ。FIG. 1 is a circuit diagram showing a typical example of a conventional logic circuit, and FIG. 2 is a circuit diagram showing an embodiment of the logic circuit of the present invention. In the figure, 1...previous stage logic circuit section, 2...
...output circuit section, 3. 5.7. 9. 9',
9", 10... Resistor, 4... Internal output stage transistor, 6... Inverter transistor, 8... Off buffer front stage transistor, 1
1...off buffer latter stage transistor, 12...
... Output transistor, 13 ... Base-collector junction capacitance, 14 ... Power supply terminal (v
oc), 15... Output terminal, 16...
Ground terminal (GND), 17...Pull-down transistor.
Claims (1)
ランジスタと、該インバータトランジスタのエミッタが
ベースに接続されたエミッタ接地の出力トランジスタと
、該出力トランジスタのコレクタと前記インバータトラ
ンジスタのコレクタとの間に介挿されベースが前記イン
バータトランジスタのコレクタに接続されたオフバッフ
ァトランジスタとを具備する論理回路において、ベース
が第１のインピーダンス素子を介し前記オフバッファト
ランジスタのエミッタに且つ第２のインピーダンス素子
を介し地気に接続され、コレクタおよびエミッタがそれ
ぞれ前記出力トランジスタのベースおよび前記インバー
タトランジスタのベースに接続されたプルダウントラン
ジスタを備える−ことを特徴とする論理回路。An inverter transistor that receives and operates the output signal of the logic circuit in the previous stage, a common emitter output transistor whose emitter is connected to the base, and an intervening device between the collector of the output transistor and the collector of the inverter transistor. an off-buffer transistor whose base is connected to the collector of the inverter transistor; A logic circuit comprising a pull-down transistor connected to the output transistor and having a collector and an emitter respectively connected to the base of the output transistor and the base of the inverter transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18348183U JPS6090938U (en) | 1983-11-28 | 1983-11-28 | logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18348183U JPS6090938U (en) | 1983-11-28 | 1983-11-28 | logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6090938U true JPS6090938U (en) | 1985-06-21 |
Family
ID=30397086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18348183U Pending JPS6090938U (en) | 1983-11-28 | 1983-11-28 | logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6090938U (en) |
-
1983
- 1983-11-28 JP JP18348183U patent/JPS6090938U/en active Pending
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