JPS60112128U - sensor circuit - Google Patents
sensor circuitInfo
- Publication number
- JPS60112128U JPS60112128U JP20052183U JP20052183U JPS60112128U JP S60112128 U JPS60112128 U JP S60112128U JP 20052183 U JP20052183 U JP 20052183U JP 20052183 U JP20052183 U JP 20052183U JP S60112128 U JPS60112128 U JP S60112128U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- circuits
- flop
- sensor
- flop circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案によるセンサー回路の一実施例を示す回
路図である。
１１〜１ｎ・・・・・・チャンネル選択スイッチ、２□
〜２ｎ、５．〜５ｎ・・・・・・フリップフロップ回路
、３１〜３ｎ・・・・・・パルス発生回路、４１〜４ｎ
・・・・・・ ゛オアデー８回路、６・・・・・
・受信チャンネル切換口 □路、７・・・・・・電
源スイツチ制御回路、８・・・・・・電源スィッチ。FIG. 1 is a circuit diagram showing an embodiment of a sensor circuit according to the present invention. 11~1n...Channel selection switch, 2□
~2n, 5. ~5n...Flip-flop circuit, 31-3n...Pulse generation circuit, 41-4n
・・・・・・ ゛orday 8 circuits, 6...
・Reception channel switching port □path, 7...Power switch control circuit, 8...Power switch.
Claims (1)
ぞれセット・リセットを繰り返すとともに自己の出力に
より他をリセットする複数の第１フリップフロップ回路
と、前記各センサーの出力信号によりそれぞれパルスを
発生する複数個のパルス発生回路と、前記各第１フリッ
プフロップ回路の出力信号をそれぞれデータ入力すると
ともに前記各パルス発生回路の出力信号を一括してクロ
ック入力とすることにより作動して被制御回路を制御す
る複数の第２フリップフロップ回路と、前記第２７リツ
プ回路のうちのいずれかがセットされている期間に於い
てのみ電源スィッチを閉に制御する電源スイツチ制御回
路とを備えたことを特徴とするセンサー回路。A plurality of sensors, a plurality of first flip-flop circuits that repeatedly set and reset each sensor according to the output signal of each sensor, and reset others with its own output, and a plurality of first flip-flop circuits that each generate a pulse according to the output signal of each sensor. and a plurality of pulse generating circuits that operate by inputting the output signals of the respective first flip-flop circuits as data and collectively inputting the output signals of the pulse generating circuits as a clock input to control the controlled circuits. a second flip-flop circuit; and a power switch control circuit that controls the power switch to close only during a period in which any one of the twenty-seventh flip-flop circuits is set. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20052183U JPS60112128U (en) | 1983-12-30 | 1983-12-30 | sensor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20052183U JPS60112128U (en) | 1983-12-30 | 1983-12-30 | sensor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60112128U true JPS60112128U (en) | 1985-07-30 |
| JPH0326677Y2 JPH0326677Y2 (en) | 1991-06-10 |
Family
ID=30761446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20052183U Granted JPS60112128U (en) | 1983-12-30 | 1983-12-30 | sensor circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60112128U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005279789A (en) * | 2004-03-26 | 2005-10-13 | Ibiden Co Ltd | Vacuum chuck for grinding/polishing |
-
1983
- 1983-12-30 JP JP20052183U patent/JPS60112128U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0326677Y2 (en) | 1991-06-10 |
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