JPS5986703U - Ferrite switch switching control circuit - Google Patents
Ferrite switch switching control circuitInfo
- Publication number
- JPS5986703U JPS5986703U JP18145682U JP18145682U JPS5986703U JP S5986703 U JPS5986703 U JP S5986703U JP 18145682 U JP18145682 U JP 18145682U JP 18145682 U JP18145682 U JP 18145682U JP S5986703 U JPS5986703 U JP S5986703U
- Authority
- JP
- Japan
- Prior art keywords
- switching
- circuit
- signal
- delay
- ferrite switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例の回路図、第２図ａ〜ｅは第１
図の動作波形図である。図において、１、 ２； １
３． １５． １６． １８・・・・・・反転アンプ、
９．１０・・・・・・駆動回路、１１・・・・・・フェ
ライトスイッチ、１２・・・・・・ＡＮＤ回路、１４．
１７・・・・・・遅延回路である。Fig. 1 is a circuit diagram of an embodiment of the present invention, and Fig. 2 a to e are a circuit diagram of an embodiment of the present invention.
FIG. 3 is an operation waveform diagram of FIG. In the figure, 1, 2; 1
3. 15. 16. 18...Inverting amplifier,
9.10... Drive circuit, 11... Ferrite switch, 12... AND circuit, 14.
17...Delay circuit.
Claims (1)
の切替動作に対応して第１および第２の切替信号を出力
する回路と、前記第１の切替回路とそれぞれ独立に制御
できる第２および第３の切替回路の各切替信号にそれぞ
れ所定遅延を与え第１および第２の遅延信号を出力する
遅延回路と、前記第１の切替信号および前記第１の遅延
信号に従って動作する第１の動作信号と前記第２の切替
信号および前記第２の遅延信号に従って動作する第２の
動作信号とを形成する論理回路と、この論理回路の第１
および第２の動作信号に対応してそれぞれ所定幅のパル
スを出力する第１および第２のパルス回路と、これらパ
ルス回路の各出力をそれぞれフェライトスイッチの一端
および他端に接続しこのフェライトスイッチの切替を駆
動する第１および第２の駆動回路とを含むフェライトス
イッチの切替制御回路。a circuit that outputs first and second switching signals in response to the switching operation of the first switching circuit that outputs on-off and mutually inverted signals; and a second switching circuit that can be controlled independently of the first switching circuit. and a delay circuit that applies a predetermined delay to each switching signal of the third switching circuit and outputs first and second delayed signals, and a first delay circuit that operates according to the first switching signal and the first delayed signal. a logic circuit that forms an operation signal and a second operation signal that operates according to the second switching signal and the second delay signal;
and a first and second pulse circuit that respectively output a pulse of a predetermined width in response to a second operation signal, and each output of these pulse circuits is connected to one end and the other end of a ferrite switch, respectively. A switching control circuit for a ferrite switch including first and second drive circuits that drive switching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18145682U JPS5986703U (en) | 1982-11-30 | 1982-11-30 | Ferrite switch switching control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18145682U JPS5986703U (en) | 1982-11-30 | 1982-11-30 | Ferrite switch switching control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5986703U true JPS5986703U (en) | 1984-06-12 |
| JPS6342562Y2 JPS6342562Y2 (en) | 1988-11-08 |
Family
ID=30393195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18145682U Granted JPS5986703U (en) | 1982-11-30 | 1982-11-30 | Ferrite switch switching control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5986703U (en) |
-
1982
- 1982-11-30 JP JP18145682U patent/JPS5986703U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6342562Y2 (en) | 1988-11-08 |
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