JPS63140732U

JPS63140732U -

Info

Publication number: JPS63140732U
Application number: JP3410887U
Authority: JP
Priority date: 1987-03-09
Filing date: 1987-03-09
Publication date: 1988-09-16

Description

[Brief explanation of drawings]

第１図はこの考案によるパルス発生装置の一実
施例を示す回路図、第２図は従来のパルス発生装
置に示す回路図である。図において、１はカウンタ、２は入力信号、３はロード信号
、４はクロツク信号、５はパルス出力信号、６は
遅延回路、７は複数の出力信号、８はセレクタ、
９は入力選択信号、１０はパルス出力信号である
。なお、図中同一符号は同一または相当部分を示
す。 FIG. 1 is a circuit diagram showing an embodiment of the pulse generator according to this invention, and FIG. 2 is a circuit diagram showing a conventional pulse generator. In the figure, 1 is a counter, 2 is an input signal, 3 is a load signal, 4 is a clock signal, 5 is a pulse output signal, 6 is a delay circuit, 7 is a plurality of output signals, 8 is a selector,
9 is an input selection signal, and 10 is a pulse output signal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A counter that inputs an initial value to the first input terminal of the three input terminals, a load signal to the second input terminal, and a clock signal to the third input terminal, counts from the initial value, and outputs an output signal; a delay circuit that inputs the output signal of the counter to an input terminal of the counter, delays the input signal, and outputs the output signal as a plurality of output signals with different delay times from a first output terminal; and a selector that inputs an input selection signal to a second input terminal, selects the input signal according to the input selection signal, and outputs the selected input signal as an output signal from the first output terminal. Device.