JPS63178920U

JPS63178920U -

Info

Publication number: JPS63178920U
Application number: JP7056087U
Authority: JP
Priority date: 1987-05-12
Filing date: 1987-05-12
Publication date: 1988-11-18

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の回路図、第２図は
第１図の各部の信号波形図、第３図は従来例の信
号波形図である。１……選択回路、２……出力回路、３……アン
ドゲート（ゲート回路）。 FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of FIG. 1, and FIG. 3 is a signal waveform diagram of a conventional example. 1... Selection circuit, 2... Output circuit, 3... AND gate (gate circuit).

Claims

[Claims for Utility Model Registration] A circuit for preventing the occurrence of glitches during the switching selection, which is provided in a system in which a plurality of asynchronous clocks are switched and selected by a switching signal as a basic clock, and which prevents the occurrence of glitches during the switching selection. a selection circuit that selects and outputs a corresponding clock from among the plurality of clocks in response to a switching signal; and a switching circuit that delays the switching timing of the switching signal based on the clock selected by the selection circuit and the switching signal. an output circuit that outputs the delayed switching signal of timing to a selection circuit and outputs a gate signal for a predetermined period before and after the switching timing of the delayed switching signal; and a clock selected by the selection circuit and the gate signal. and a gate circuit which outputs the selected clock as a basic clock except for a period corresponding to the gate signal.