JPS63178920U - - Google Patents
Info
- Publication number
- JPS63178920U JPS63178920U JP7056087U JP7056087U JPS63178920U JP S63178920 U JPS63178920 U JP S63178920U JP 7056087 U JP7056087 U JP 7056087U JP 7056087 U JP7056087 U JP 7056087U JP S63178920 U JPS63178920 U JP S63178920U
- Authority
- JP
- Japan
- Prior art keywords
- switching
- circuit
- clock
- signal
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第1図は本考案の一実施例の回路図、第2図は
第1図の各部の信号波形図、第3図は従来例の信
号波形図である。
1……選択回路、2……出力回路、3……アン
ドゲート(ゲート回路)。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of FIG. 1, and FIG. 3 is a signal waveform diagram of a conventional example. 1... Selection circuit, 2... Output circuit, 3... AND gate (gate circuit).
Claims (1)
換選択して基本クロツクとするシステムに備えら
れ、前記切換選択の際のグリツジの発生を防止す
る回路であつて、 遅延切換信号に応答して前記複数のクロツクの
内から対応するクロツクを選択出力する選択回路
と、 この選択回路で選択されたクロツクおよび前記
切換信号に基づいて、切換信号の切換タイミング
よりも遅延した切換タイミングの前記遅延切換信
号を選択回路に出力するとともに、この遅延切換
信号の切換タイミングの前後の所定期間に亘つて
ゲート信号を出力する出力回路と、 前記選択回路で選択されたクロツクおよび前記
ゲート信号が与えられ、この選択されたクロツク
を、ゲート信号に対応する期間を除いて基本クロ
ツクとして出力するゲート回路とを備えることを
特徴とするグリツジ防止回路。[Claims for Utility Model Registration] A circuit for preventing the occurrence of glitches during the switching selection, which is provided in a system in which a plurality of asynchronous clocks are switched and selected by a switching signal as a basic clock, and which prevents the occurrence of glitches during the switching selection. a selection circuit that selects and outputs a corresponding clock from among the plurality of clocks in response to a switching signal; and a switching circuit that delays the switching timing of the switching signal based on the clock selected by the selection circuit and the switching signal. an output circuit that outputs the delayed switching signal of timing to a selection circuit and outputs a gate signal for a predetermined period before and after the switching timing of the delayed switching signal; and a clock selected by the selection circuit and the gate signal. and a gate circuit which outputs the selected clock as a basic clock except for a period corresponding to the gate signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7056087U JPS63178920U (en) | 1987-05-12 | 1987-05-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7056087U JPS63178920U (en) | 1987-05-12 | 1987-05-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63178920U true JPS63178920U (en) | 1988-11-18 |
Family
ID=30912306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7056087U Pending JPS63178920U (en) | 1987-05-12 | 1987-05-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63178920U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010225057A (en) * | 2009-03-25 | 2010-10-07 | Seiko Epson Corp | Clock switching circuit, integrated circuit device, and electronic device |
-
1987
- 1987-05-12 JP JP7056087U patent/JPS63178920U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010225057A (en) * | 2009-03-25 | 2010-10-07 | Seiko Epson Corp | Clock switching circuit, integrated circuit device, and electronic device |
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