JPS6416737U - - Google Patents
Info
- Publication number
- JPS6416737U JPS6416737U JP11177787U JP11177787U JPS6416737U JP S6416737 U JPS6416737 U JP S6416737U JP 11177787 U JP11177787 U JP 11177787U JP 11177787 U JP11177787 U JP 11177787U JP S6416737 U JPS6416737 U JP S6416737U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- circuit
- signal
- clock signal
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 2
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案に係る遅延リセツト装置の一実
施例を示すブロツク図、第２図は第１図に示した
実施例を適用した交換機におけるタイムスイツチ
ユニツトの構成を示すブロツク図、第３図ａ，ｂ
，ｃおよびｄは第１図に示した実施例における各
信号をそれぞれ示すタイミングチヤート、第４図
は交換機における従来のタイムスイツチユニツト
の構成を示すブロツク図である。
１…クロツク発生回路、２…遅延リセツト回路
、３…アンド回路、４…オア回路、１１…タイム
スイツチユニツト、１２…会議回路、１３…タイ
ミングスイツチ回路、１４…タイムスイツチ制御
回路、１６…リセツト回路、１７…リセツトスイ
ツチ、１８…ＣＰＵ、１９…クロツク原振。
FIG. 1 is a block diagram showing an embodiment of a delay reset device according to the present invention, FIG. 2 is a block diagram showing the configuration of a time switch unit in an exchange to which the embodiment shown in FIG. 1 is applied, and FIG. a, b
, c and d are timing charts showing respective signals in the embodiment shown in FIG. 1, and FIG. 4 is a block diagram showing the configuration of a conventional time switch unit in an exchange. DESCRIPTION OF SYMBOLS 1...Clock generation circuit, 2...Delay reset circuit, 3...AND circuit, 4...OR circuit, 11...time switch unit, 12...conference circuit, 13...timing switch circuit, 14...time switch control circuit, 16...reset circuit , 17...Reset switch, 18...CPU, 19...Clock source.
Claims (1)
リセツト型回路の遅延リセツト装置において、 リセツト信号を送出するリセツト回路と、 前記リセツト信号によつてリセツトされクロツ
ク信号の発生を停止し、リセツト解除によりクロ
ツク信号の発生を開始するクロツク発生回路と、 前記リセツト回路から発生されるリセツト信号
を所定の時間伸長させて前記同期リセツト型回路
に加える遅延手段と を備えたことを特徴とする遅延リセツト装置。[Claims for Utility Model Registration] A delay reset device for a synchronous reset type circuit that requires input of a clock signal at the time of reset, comprising a reset circuit that sends out a reset signal, and a reset circuit that is reset by the reset signal to stop generating the clock signal. The present invention is characterized in that it comprises a clock generation circuit that starts generating a clock signal upon release of the reset, and a delay means that extends the reset signal generated from the reset circuit by a predetermined time and applies it to the synchronous reset type circuit. Delayed reset device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11177787U JPS6416737U (en) | 1987-07-21 | 1987-07-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11177787U JPS6416737U (en) | 1987-07-21 | 1987-07-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6416737U true JPS6416737U (en) | 1989-01-27 |
Family
ID=31350127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11177787U Pending JPS6416737U (en) | 1987-07-21 | 1987-07-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6416737U (en) |
-
1987
- 1987-07-21 JP JP11177787U patent/JPS6416737U/ja active Pending
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