JPS6215142U - - Google Patents

Info

Publication number
JPS6215142U
JPS6215142U JP10462285U JP10462285U JPS6215142U JP S6215142 U JPS6215142 U JP S6215142U JP 10462285 U JP10462285 U JP 10462285U JP 10462285 U JP10462285 U JP 10462285U JP S6215142 U JPS6215142 U JP S6215142U
Authority
JP
Japan
Prior art keywords
amount control
variable delay
delay amount
control means
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10462285U
Other languages
Japanese (ja)
Other versions
JPH067469Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10462285U priority Critical patent/JPH067469Y2/en
Publication of JPS6215142U publication Critical patent/JPS6215142U/ja
Application granted granted Critical
Publication of JPH067469Y2 publication Critical patent/JPH067469Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示すブロツク図、第
2図は第1図における可変遅延装置の実施例を示
すブロツク図、第3図は第1図の動作を示すフロ
ーチヤート、第4図は従来のノーマルトラツキン
グ調整回路のブロツク図、第5図は従来のスロー
トラツキング調整回路の実施例を示すブロツク図
、第6図は従来の擬似垂直同期信号を作る回路の
ブロツク図である。 なお図面に用いた符号において、11a,11
b,11c……可変遅延回路、16……マイコン
、17,18……スイツチである。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the variable delay device in FIG. 1, FIG. 3 is a flowchart showing the operation of FIG. 1, and FIG. 4 5 is a block diagram of a conventional normal tracking adjustment circuit, FIG. 5 is a block diagram showing an embodiment of a conventional slow tracking adjustment circuit, and FIG. 6 is a block diagram of a conventional circuit for generating a pseudo vertical synchronization signal. In addition, in the symbols used in the drawings, 11a, 11
b, 11c... variable delay circuit, 16... microcomputer, 17, 18... switch.

Claims (1)

【実用新案登録請求の範囲】 動作モードに応じて選択的に用いられる複数の
可変遅延手段、 上記複数の可変遅延手段に対して共通に用いら
れる遅延量制御手段、 上記遅延量制御手段から得られる制御信号を、
動作モードに応じて選択された可変遅延手段に供
給する手段、 を夫々具備して成る電子機器。
[Claims for Utility Model Registration] A plurality of variable delay means selectively used depending on the operation mode, a delay amount control means commonly used for the plurality of variable delay means, and a delay amount control means obtained from the delay amount control means. control signal,
An electronic device comprising: means for supplying a variable delay means selected according to an operating mode.
JP10462285U 1985-07-09 1985-07-09 Video signal playback device Expired - Lifetime JPH067469Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10462285U JPH067469Y2 (en) 1985-07-09 1985-07-09 Video signal playback device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10462285U JPH067469Y2 (en) 1985-07-09 1985-07-09 Video signal playback device

Publications (2)

Publication Number Publication Date
JPS6215142U true JPS6215142U (en) 1987-01-29
JPH067469Y2 JPH067469Y2 (en) 1994-02-23

Family

ID=30978285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10462285U Expired - Lifetime JPH067469Y2 (en) 1985-07-09 1985-07-09 Video signal playback device

Country Status (1)

Country Link
JP (1) JPH067469Y2 (en)

Also Published As

Publication number Publication date
JPH067469Y2 (en) 1994-02-23

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