JPS63153178U - - Google Patents
Info
- Publication number
- JPS63153178U JPS63153178U JP4507387U JP4507387U JPS63153178U JP S63153178 U JPS63153178 U JP S63153178U JP 4507387 U JP4507387 U JP 4507387U JP 4507387 U JP4507387 U JP 4507387U JP S63153178 U JPS63153178 U JP S63153178U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- integrator
- reference signal
- input
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 230000010354 integration Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案に係る同期検波回路の一実施例
を示す構成ブロツク図、第２図は第１図装置の動
作を説明するためのタイムチヤート、第３図は本
考案に係る同期検波回路の第２の実施例を示す要
部構成ブロツク図、第４図は従来の同期検波回路
の一例を示す構成ブロツク図である。
２…掛算器、４…Ａ／Ｄ変換器、１４，１６…
スイツチ手段、１５…積分器、１７…制御回路、
Ｅ４…入力信号、Ｅｓ…参照信号。
Fig. 1 is a configuration block diagram showing an embodiment of the synchronous detection circuit according to the present invention, Fig. 2 is a time chart for explaining the operation of the apparatus shown in Fig. 1, and Fig. 3 is a synchronous detection circuit according to the invention. FIG. 4 is a block diagram showing an example of a conventional synchronous detection circuit. 2... Multiplier, 4... A/D converter, 14, 16...
Switch means, 15... Integrator, 17... Control circuit,
E4 ...input signal, Es ...reference signal.
Claims (1)
いて信号検出を行う同期検波回路において、入力
信号に関係する信号を入力し参照信号に同期して
動作する掛算器と、この掛算器の出力に関係する
信号を入力する積分器と、この積分器の積分動作
を制御するスイツチ手段と、前記積分器出力を入
力するＡ／Ｄ変換器と、前記スイツチ手段とＡ／
Ｄ変換器の動作を制御する制御回路とを備えると
ともに、積分器が参照信号の半周期の整数倍の積
分時間を有するように構成したことを特徴とする
同期検波回路。 In a synchronous detection circuit that detects a signal using a reference signal that is phase-synchronized with the input signal, there is a multiplier that receives a signal related to the input signal and operates in synchronization with the reference signal, and a multiplier that operates in synchronization with the reference signal. an integrator to which related signals are input; a switch means to control the integration operation of the integrator; an A/D converter to which the integrator output is input;
1. A synchronous detection circuit comprising: a control circuit for controlling the operation of a D converter; and an integrator configured to have an integration time that is an integral multiple of a half period of a reference signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4507387U JPS63153178U (en) | 1987-03-27 | 1987-03-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4507387U JPS63153178U (en) | 1987-03-27 | 1987-03-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63153178U true JPS63153178U (en) | 1988-10-07 |
Family
ID=30863481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4507387U Pending JPS63153178U (en) | 1987-03-27 | 1987-03-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63153178U (en) |
-
1987
- 1987-03-27 JP JP4507387U patent/JPS63153178U/ja active Pending